Taito TC0190 pinout: Difference between revisions

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m (slight rephrase for clarity)
m (35, 36 no internal connection. 20, 31 internally both ground)
 
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[[Category:Pinouts]]
[[Category:Pinouts]]
Taito TC0190: 0.6" high-density PDIP (Canonically [[iNES Mapper 033]])
Taito TC0190: 0.6" 40-pin high-density PDIP (Canonically [[iNES Mapper 033]])
                   .--\/--.
                   .--\/--.
   (s) PRG D0 -> |01  40| -- Vcc
   (fr) CPU D0 -> |01  40| -- Vcc
   (s) PRG D1 -> |02  39| <- PRG R/W (F)
   (fr) CPU D1 -> |02  39| <- R/W (f)
   (s) PRG D2 -> |03  38| <- /ROMSEL (F)
   (fr) CPU D2 -> |03  38| <- /ROMSEL (f)
   (s) PRG D3 -> |04  37| <- M2 (F)
   (fr) CPU D3 -> |04  37| <- M2 (f)
   (s) PRG D4 -> |05  36| ?? NC
   (fr) CPU D4 -> |05  36| -- n/c
   (s) PRG D5 -> |06  35| ?? NC
   (fr) CPU D5 -> |06  35| -- n/c
   (s) PRG D6 -> |07  34| <- PPU A10 (F)
   (fr) CPU D6 -> |07  34| <- PPU A10 (f)
   (s) PRG D7 -> |08  33| <- PPU A11 (F)
   (fr) CPU D7 -> |08  33| <- PPU A11 (f)
   (r) PRG A13 <- |09  32| <- PPU A12 (F)
   (r) PRG A13 <- |09  32| <- PPU A12 (f)
   (r) PRG A14 <- |10  31| ?? GND
   (r) PRG A14 <- |10  31| -- GND
   (r) PRG A15 <- |11  30| -> CIRAM A10 (F)
   (r) PRG A15 <- |11  30| -> CIRAM A10 (f)
   (r) PRG A16 <- |12  29| -> CHR A10 (r)
   (r) PRG A16 <- |12  29| -> CHR A10 (r)
   (r) PRG A17 <- |13  28| -> CHR A11 (r)
   (r) PRG A17 <- |13  28| -> CHR A11 (r)
   (r) PRG A18 <- |14  27| -> CHR A12 (r)
   (r) PRG A18 <- |14  27| -> CHR A12 (r)
   (s) PRG A0 -> |15  26| -> CHR A13 (r)
   (fr) CPU A0 -> |15  26| -> CHR A13 (r)
   (s) PRG A1 -> |16  25| -> CHR A14 (r)
   (fr) CPU A1 -> |16  25| -> CHR A14 (r)
   (F) PRG A13 -> |17  24| -> CHR A15 (r)
   (f) CPU A13 -> |17  24| -> CHR A15 (r)
   (F) PRG A14 -> |18  23| -> CHR A16 (r)
   (f) CPU A14 -> |18  23| -> CHR A16 (r)
   (r) PRG /CE <- |19  22| -> CHR A17 (r)
   (r) PRG /CE <- |19  22| -> CHR A17 (r)
           GND -- |20  21| ?? NC
           GND -- |20  21| -> CHR A18 (r)
                   '------'
                   '------'


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                   PAL16R4
                   PAL16R4
                   --\/--
                   --\/--
   (F) /ROMSEL -> |01  20| -- Vcc
   (f) /ROMSEL -> |01  20| -- Vcc
   (F) /ROMSEL -> |02  19| -> CIRAM A10 (F)
   (f) /ROMSEL -> |02  19| -> CIRAM A10 (f)
   (F) PRG R/W -> |03  18| ?? NC
   (f)     R/W -> |03  18| ?? NC
   (F) PRG A14 -> |04  17| -> NC
   (f) CPU A14 -> |04  17| -> NC (latched value written to D6)
   (F) PRG A13 -> |05  16| -> NC
   (f) CPU A13 -> |05  16| -> NC
   (F) PRG A1 -> |06  15| -> NC
   (fr) CPU A1 -> |06  15| -> NC
   (F) PRG A0 -> |07  14| -> NC
   (fr) CPU A0 -> |07  14| -> NC
   (F) PPU A11 -> |08  13| <- PRG D6 (s)
   (f) PPU A11 -> |08  13| <- CPU D6 (fr)
   (F) PPU A10 -> |09  12| -> to TC0190 pin 38
   (f) PPU A10 -> |09  12| -> to TC0190 pin 38
           GND -- |10  11| <- GND (PAL /OE signal)
           GND -- |10  11| <- GND (PAL /OE signal)
                   ------
                   ------


PALs allow the programming of arbitrarily logic functions, but in the PAL16R4, pins 1 and 11 have fixed functionality. This is why /ROMSEL is connected to both pins 1 and pin 2: pin 1 can ''only'' be used as a clock input to latch the value of D6, but /ROMSEL is also connected to pin 2 so that the PAL can fail to pass through the write to the TC0190 when the CPU writes to $E000.
[[wikipedia:Programmable_Array_Logic|PAL]]s allow the programming of arbitrary logic functions, but in the PAL16R4, pins 1 and 11 have fixed functionality. This is why /ROMSEL is connected to both pins 1 and pin 2: pin 1 can ''only'' be used as a clock input to latch the value of D6, but /ROMSEL is also connected to pin 2 so that the PAL can fail to pass through the write to the TC0190 when the CPU writes to $E000.

Latest revision as of 21:46, 18 February 2020

Taito TC0190: 0.6" 40-pin high-density PDIP (Canonically iNES Mapper 033) 

                 .--\/--.
  (fr) CPU D0 -> |01  40| -- Vcc
  (fr) CPU D1 -> |02  39| <- R/W (f)
  (fr) CPU D2 -> |03  38| <- /ROMSEL (f)
  (fr) CPU D3 -> |04  37| <- M2 (f)
  (fr) CPU D4 -> |05  36| -- n/c
  (fr) CPU D5 -> |06  35| -- n/c
  (fr) CPU D6 -> |07  34| <- PPU A10 (f)
  (fr) CPU D7 -> |08  33| <- PPU A11 (f)
  (r) PRG A13 <- |09  32| <- PPU A12 (f)
  (r) PRG A14 <- |10  31| -- GND
  (r) PRG A15 <- |11  30| -> CIRAM A10 (f)
  (r) PRG A16 <- |12  29| -> CHR A10 (r)
  (r) PRG A17 <- |13  28| -> CHR A11 (r)
  (r) PRG A18 <- |14  27| -> CHR A12 (r)
  (fr) CPU A0 -> |15  26| -> CHR A13 (r)
  (fr) CPU A1 -> |16  25| -> CHR A14 (r)
  (f) CPU A13 -> |17  24| -> CHR A15 (r)
  (f) CPU A14 -> |18  23| -> CHR A16 (r)
  (r) PRG /CE <- |19  22| -> CHR A17 (r)
          GND -- |20  21| -> CHR A18 (r)
                 '------'

Some boards added a PAL to the TC0190. As far as we can tell, the only purpose of the PAL was to move the mirroring control bit. This becomes a subset of iNES Mapper 048 instead: 

TC0190 pin 30: (was CIRAM A10) now NC
TC0190 pin 38: (was /ROMSEL) now from PAL pin 12

                 PAL16R4
                  --\/--
  (f) /ROMSEL -> |01  20| -- Vcc
  (f) /ROMSEL -> |02  19| -> CIRAM A10 (f)
  (f)     R/W -> |03  18| ?? NC
  (f) CPU A14 -> |04  17| -> NC (latched value written to D6)
  (f) CPU A13 -> |05  16| -> NC
  (fr) CPU A1 -> |06  15| -> NC
  (fr) CPU A0 -> |07  14| -> NC
  (f) PPU A11 -> |08  13| <- CPU D6 (fr)
  (f) PPU A10 -> |09  12| -> to TC0190 pin 38
          GND -- |10  11| <- GND (PAL /OE signal)
                  ------

PALs allow the programming of arbitrary logic functions, but in the PAL16R4, pins 1 and 11 have fixed functionality. This is why /ROMSEL is connected to both pins 1 and pin 2: pin 1 can only be used as a clock input to latch the value of D6, but /ROMSEL is also connected to pin 2 so that the PAL can fail to pass through the write to the TC0190 when the CPU writes to $E000.

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