NES 2.0 Mapper 285: Difference between revisions
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[[Category:Multicart mappers | {{DEFAULTSORT:285}}[[Category:Multicart mappers]][[Category:Mappers with CHR RAM]]'''NES 2.0 Mapper 285''' is used for the ''A65AS'' and ''JY-066'' multicarts. The UNIF board name for both incompatible variants is '''BMC-A65AS'''. | ||
=Banks= | =Banks= | ||
Line 7: | Line 7: | ||
* PPU $0000-$1FFF: 8 KiB unbanked CHR-RAM | * PPU $0000-$1FFF: 8 KiB unbanked CHR-RAM | ||
=Data Latch | =Data Latch (CPU $8000-$FFFF)= | ||
==A65AS (Submapper 0)== | |||
Bit 7654 3210 | Bit 7654 3210 | ||
--------- | --------- | ||
SPMO OBBB | |||
|||| |+++- Select 16 KiB inner PRG-ROM bank at CPU $8000-$BFFF in 16 KiB mode (bit 6=0) | |||
|||| |++-- Select 32 KiB PRG-ROM bank at CPU $8000-$FFFF in 32 KiB mode (bit 6=1) | |||
|||+-+---- Select 128 KiB outer PRG-ROM bank at CPU $8000-$FFFF in 16 KiB mode (bit 6=0) | |||
||+------- Select nametable mirroring | |||
|| 0: Vertical (bit 7=0)/Single-screen, page 0 (bit 7=1) | |||
|| 1: Horizontal (bit 7=0)/Single-screen, page 1 (bit 7=1) | |||
|+-------- Select PRG banking mode | |||
| 0: 16 KiB | |||
| 1: 32 KiB | |||
+--------- Select nametable mirroring type | |||
0: Horizontal/vertical (selected via bit 3) | |||
1: Single-screen (selected via bit 5) | |||
==JY-066 (Submapper 1)== | |||
Bit 7654 3210 | |||
--------- | |||
SPMO HBBB | |||
|||| |+++- Select 16 KiB inner PRG-ROM bank at CPU $8000-$BFFF in 16 KiB mode (bit 6=0) | |||| |+++- Select 16 KiB inner PRG-ROM bank at CPU $8000-$BFFF in 16 KiB mode (bit 6=0) | ||
|||| |++-- Select 32 KiB PRG-ROM bank at CPU $8000-$FFFF in 32 KiB mode (bit 6=1) | |||| |++-- Select 32 KiB PRG-ROM bank at CPU $8000-$FFFF in 32 KiB mode (bit 6=1) |
Latest revision as of 14:16, 17 February 2024
NES 2.0 Mapper 285 is used for the A65AS and JY-066 multicarts. The UNIF board name for both incompatible variants is BMC-A65AS.
Banks
- CPU $8000-$BFFF: In 16 KiB mode: 16 KiB switchable inner bank, 128 KiB switchable outer bank
- CPU $C000-$FFFF: In 16 KiB mode: 16 KiB fixed inner bank 7, 128 KiB switchable outer bank
- CPU $8000-$FFFF: In 32 KiB mode: 32 KiB switchable bank
- PPU $0000-$1FFF: 8 KiB unbanked CHR-RAM
Data Latch (CPU $8000-$FFFF)
A65AS (Submapper 0)
Bit 7654 3210 --------- SPMO OBBB |||| |+++- Select 16 KiB inner PRG-ROM bank at CPU $8000-$BFFF in 16 KiB mode (bit 6=0) |||| |++-- Select 32 KiB PRG-ROM bank at CPU $8000-$FFFF in 32 KiB mode (bit 6=1) |||+-+---- Select 128 KiB outer PRG-ROM bank at CPU $8000-$FFFF in 16 KiB mode (bit 6=0) ||+------- Select nametable mirroring || 0: Vertical (bit 7=0)/Single-screen, page 0 (bit 7=1) || 1: Horizontal (bit 7=0)/Single-screen, page 1 (bit 7=1) |+-------- Select PRG banking mode | 0: 16 KiB | 1: 32 KiB +--------- Select nametable mirroring type 0: Horizontal/vertical (selected via bit 3) 1: Single-screen (selected via bit 5)
JY-066 (Submapper 1)
Bit 7654 3210 --------- SPMO HBBB |||| |+++- Select 16 KiB inner PRG-ROM bank at CPU $8000-$BFFF in 16 KiB mode (bit 6=0) |||| |++-- Select 32 KiB PRG-ROM bank at CPU $8000-$FFFF in 32 KiB mode (bit 6=1) |||| +---- Select nametable mirroring if bit 7=0 |||| 0: Vertical |||| 1: Horizontal ||++------ Select 128 KiB outer PRG-ROM bank at CPU $8000-$FFFF in 16 KiB mode (bit 6=0) ||+------- Select nametable mirroring if bit 7=1 || 0: Single-screen, page 0 || 1: Single-screen, page 1 |+-------- Select PRG banking mode | 0: 16 KiB | 1: 32 KiB +--------- Select nametable mirroring type 0: Horizontal/vertical (selected via bit 3) 1: Single-screen (selected via bit 5)