Bandai Datach pinout: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(copy from Naruko's documentation)
 
(Naruko's numbering for pins 17-32 does not follow the actual pin numbers etched on cartridge's boards)
 
(2 intermediate revisions by 2 users not shown)
Line 1: Line 1:
[[Category:pinouts]]
Bandai Datach: 32-pin 0.1" card edge ([[iNES Mapper 157]])
Bandai Datach: 32-pin 0.1" card edge ([[iNES Mapper 157]])


  1 o external I2C SCL |17 s  +5V
  **CHR A13 <- |  1 32 | -- +5V
  2 o PRG A16         |18 o sub cartridge expansion?
    PRG A16 <- 2 31 | -> ??CHR A12??
  3 o PRG A15         |19 o PRG A17
    PRG A15 <- 3 30 | -> PRG A17
  4 o CPU A12         |20 o PRG A14
    CPU A12 <- 4 29 | -> PRG A14
  5 o CPU A7           |21 o CPU A13
      CPU A7 <- 5 28 | -> CPU A13
  6 o CPU A6           |22 o CPU A8
      CPU A6 <- 6 27 | -> CPU A8
  7 o CPU A5           |23 o CPU A9
      CPU A5 <- 7 26 | -> CPU A9
  8 o CPU A4           |24 o CPU A11
      CPU A4 <- 8 25 | -> CPU A11
  9 o CPU A3           |25 o Program EN#
      CPU A3 <- 9 24 | -> /ExternalROMRead
10 o CPU A2           |26 o  CPU ROM A10
      CPU A2 <- | 10 23 | -> CPU A10
11 o CPU A1           |27 IO I2C SDA
      CPU A1 <- | 11 22 | <> I2C SDA
12 o CPU A0           |28 i  CPU D7
      CPU A0 <- | 12 21 | <> CPU D7
13 i CPU D0           |29 i  CPU D6
      CPU D0 <> | 13 20 | <> CPU D6
14 i CPU D1           |30 i  CPU D5
      CPU D1 <> | 14 19 | <> CPU D5
15 i CPU D2           |31 i  CPU D4
      CPU D2 <> | 15 18 | <> CPU D4
16 s GND              |32 i  CPU D3
      GND    -- | 16 17 | <> CPU D3
 
Notes:
* Pin 1 is used for the external I²C EEPROM clock.
* Pin 31 is Naruko's educated guess


This is almost the standard JEDEC ROM pin order.
This is almost the standard JEDEC ROM pin order.


Source: [//seesaawiki.jp/famicomcartridge/d/Bandai%20Datach Naruko]
Source: [//seesaawiki.jp/famicomcartridge/d/Bandai%20Datach Naruko]

Latest revision as of 15:22, 8 May 2023

Bandai Datach: 32-pin 0.1" card edge (iNES Mapper 157)

  **CHR A13 <- |  1 32 | -- +5V
    PRG A16 <- |  2 31 | -> ??CHR A12??
    PRG A15 <- |  3 30 | -> PRG A17
    CPU A12 <- |  4 29 | -> PRG A14
     CPU A7 <- |  5 28 | -> CPU A13
     CPU A6 <- |  6 27 | -> CPU A8
     CPU A5 <- |  7 26 | -> CPU A9
     CPU A4 <- |  8 25 | -> CPU A11
     CPU A3 <- |  9 24 | -> /ExternalROMRead
     CPU A2 <- | 10 23 | -> CPU A10
     CPU A1 <- | 11 22 | <> I2C SDA
     CPU A0 <- | 12 21 | <> CPU D7
     CPU D0 <> | 13 20 | <> CPU D6
     CPU D1 <> | 14 19 | <> CPU D5
     CPU D2 <> | 15 18 | <> CPU D4
     GND    -- | 16 17 | <> CPU D3

Notes:

  • Pin 1 is used for the external I²C EEPROM clock.
  • Pin 31 is Naruko's educated guess

This is almost the standard JEDEC ROM pin order.

Source: Naruko