C5052-13 pinout: Difference between revisions

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(Created page with " .--\/--. +5V -- |01 40| <- CPU A0 mode -> |02 39| <- CPU A1 PRG A13 <- |03 38| <- M2 PRG A14 <- |04 37| <- CPU A12 PRG A15 <- |05 36| <- CP...")
 
(assignment to category: pinous)
Line 25: Line 25:
References:
References:
[[https://forums.nesdev.org/viewtopic.php?f=9&t=19248 BBS]]
[[https://forums.nesdev.org/viewtopic.php?f=9&t=19248 BBS]]
[[Category: pinouts]]

Revision as of 18:37, 9 February 2020

            .--\/--. 
     +5V -- |01  40| <- CPU A0
    mode -> |02  39| <- CPU A1
 PRG A13 <- |03  38| <- M2
 PRG A14 <- |04  37| <- CPU A12
 PRG A15 <- |05  36| <- CPU A13
 PRG A16 <- |06  35| <- CPU A14
 PRG A17 <- |07  34| <- CPU D4
 PRG A18 <- |08  33| <- CPU D5
 PRG /CE <- |09  32| <- CPU /ROMSEL
WRAM +CE <- |10  31| <- CPU D6
 CHR A10 <- |11  30| <- CPU D7
 CHR A11 <- |12  29| <- CPU D0
 CHR A12 <- |13  28| <- CPU R/!W
 CHR A13 <- |14  27| -> CIRAM A10
 CHR A14 <- |15  26| <- CPU D1
 CHR A15 <- |16  25| <- CPU D2
 CHR A16 <- |17  24| <- CPU D3
 CHR A17 <- |18  23| -> PPU A12
    /IRQ <- |19  22| -> PPU A11
     GND -- |20  21| -> PPU A10
            `------' 
            C5052-13 

References: [BBS]