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| =Registers= | | =Registers= |
| ==Read Serial EEPROM ($6000-$7FFF read)==
| | All registers function the same way as [[INES Mapper 016]], submapper 5, except that the serial EEPROM is not a 24C02 but a 24C01. Bandai's developers consistently thought the 24C01 was a little-endian device, and their code clocks in address and data bytes assuming this. However, it's actually a big-endian device, and a multi-byte read or write from EEPROM will increment the address accordingly. |
| Mask: $E000
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| 7 bit 0
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| ---- ----
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| xxxE xxxx
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| |||| ||||
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| +++|-++++- Open bus
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| +------ Data out from I²C EEPROM
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| ==CHR-ROM Bank Select ($8000-$8007 write)==
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| Mask: $800F
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|
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| 7 bit 0
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| ---- ----
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| CCCC CCCC
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| |||| ||||
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| ++++-++++-- 1 KiB CHR-ROM bank number
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| * $xxx0: Select 1 KiB CHR-ROM bank at PPU $0000-$03FF
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| * $xxx1: Select 1 KiB CHR-ROM bank at PPU $0400-$07FF
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| * $xxx2: Select 1 KiB CHR-ROM bank at PPU $0800-$0BFF
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| * $xxx3: Select 1 KiB CHR-ROM bank at PPU $0C00-$0FFF
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| * $xxx4: Select 1 KiB CHR-ROM bank at PPU $1000-$13FF
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| * $xxx5: Select 1 KiB CHR-ROM bank at PPU $1400-$17FF
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| * $xxx6: Select 1 KiB CHR-ROM bank at PPU $1800-$1BFF
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| * $xxx7: Select 1 KiB CHR-ROM bank at PPU $1C00-$1FFF
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| ==PRG-ROM Bank Select ($8008 write)==
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| Mask: $800F
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| 7 bit 0
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| ---- ----
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| .... PPPP
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| ||||
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| ++++-- Select 16 KiB PRG-ROM bank at CPU $8000-$BFFF
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| ==Nametable Mirroring Type Select ($8009 write)==
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| Mask: $800F
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| 7 bit 0
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| ---- ----
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| .... ..MM
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| ||
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| ++-- Select nametable mirroring type
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| 0: Vertical
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| 1: Horizontal
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| 2: One-screen, page 0
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| 3: One-screen, page 1
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| ==IRQ Control ($800A write)==
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| Mask: $800F
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|
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| 7 bit 0
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| ---- ----
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| .... ...C
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| +-- IRQ counter control
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| 0: Counting disabled
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| 1: Counting enabled
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| * Writing to this register acknowledges a pending IRQ, and copies the latch to the actual counter.
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| * If a write to this register enables counting while the counter is holding a value of zero, an IRQ is generated immediately.
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| ==IRQ Latch ($800B-$800C write)==
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| Mask: $800F
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| $C $B
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| 7 bit 0 7 bit 0
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| ---- ---- ---- ----
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| CCCC CCCC CCCC CCCC
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| |||| |||| |||| ||||
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| ++++-++++--++++-++++-- Counter value (little-endian)
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| * If counting is enabled, the counter decreases on every M2 cycle. When it holds a value of zero, an IRQ is generated.
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| * These registers modify a latch that will only be copied to the actual counter when register $xxxA is written to.
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| ==EEPROM Control ($800D write)==
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| Mask: $800F
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| 7 bit 0
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| ---- ----
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| RDC. ....
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| |||
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| ||+-------- I²C SCL
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| |+--------- I²C SDA
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| +---------- Direction bit (1=Enable Read)
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| | |
| * This register only has an effect if a 24C01 EEPROM is present.
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| * Please refer to generic I²C tutorials and the 24C01 datasheet on how to operate or emulate this register correctly.
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| * Bandai's developers consistently thought the 24C01 was a little-endian device, and their code clocks in address and data bytes assuming this. However, it's actually a big-endian device, and a multi-byte read or write from EEPROM will increment the address accordingly.
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iNES Mapper 159 is used for Bandai FCG boards with an LZ93D50 ASIC and a 128-byte serial EEPROM (24C01). The 128 bytes must be denoted as PRG-NVRAM in the NES 2.0 header using byte value $10.
Game List
- Dragon Ball Z: Kyoushuu! Saiya-jin
- Magical Taruruuto-kun: Fantastic World!!
- Magical Taruruuto-kun 2: Mahou Daibouken
- SD Gundam Gaiden - Knight Gundam Monogatari
Banks
- CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
- CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last bank
- PPU $0000-$03FF: 1 KiB switchable CHR ROM bank
- PPU $0400-$07FF: 1 KiB switchable CHR ROM bank
- PPU $0800-$0BFF: 1 KiB switchable CHR ROM bank
- PPU $0C00-$0FFF: 1 KiB switchable CHR ROM bank
- PPU $1000-$13FF: 1 KiB switchable CHR ROM bank
- PPU $1400-$17FF: 1 KiB switchable CHR ROM bank
- PPU $1800-$1BFF: 1 KiB switchable CHR ROM bank
- PPU $1C00-$1FFF: 1 KiB switchable CHR ROM bank
Registers
All registers function the same way as INES Mapper 016, submapper 5, except that the serial EEPROM is not a 24C02 but a 24C01. Bandai's developers consistently thought the 24C01 was a little-endian device, and their code clocks in address and data bytes assuming this. However, it's actually a big-endian device, and a multi-byte read or write from EEPROM will increment the address accordingly.
