Bandai Datach pinout: Difference between revisions
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(copy from Naruko's documentation) |
(reformat) |
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Bandai Datach: 32-pin 0.1" card edge ([[iNES Mapper 157]]) | Bandai Datach: 32-pin 0.1" card edge ([[iNES Mapper 157]]) | ||
**CHR A13 <- | 1 17 | -- +5V | |||
PRG A16 <- | 2 18 | -> ??CHR A12?? | |||
PRG A15 <- | 3 19 | -> PRG A17 | |||
CPU A12 <- | 4 20 | -> PRG A14 | |||
CPU A7 <- | 5 21 | -> CPU A13 | |||
CPU A6 <- | 6 22 | -> CPU A8 | |||
CPU A5 <- | 7 23 | -> CPU A9 | |||
CPU A4 <- | 8 24 | -> CPU A11 | |||
CPU A3 <- | 9 25 | -> /ExternalROMRead | |||
CPU A2 <- | 10 26 | -> CPU A10 | |||
CPU A1 <- | 11 27 | <> I2C SDA | |||
CPU A0 <- | 12 28 | <> CPU D7 | |||
CPU D0 <> | 13 29 | <> CPU D6 | |||
CPU D1 <> | 14 30 | <> CPU D5 | |||
CPU D2 <> | 15 31 | <> CPU D4 | |||
GND -- | 16 32 | <> CPU D3 | |||
Notes: | |||
* Pin 1 is used for the external I²C EEPROM clock. | |||
* Pin 18 is Naruko's educated guess | |||
This is almost the standard JEDEC ROM pin order. | This is almost the standard JEDEC ROM pin order. | ||
Source: [//seesaawiki.jp/famicomcartridge/d/Bandai%20Datach Naruko] | Source: [//seesaawiki.jp/famicomcartridge/d/Bandai%20Datach Naruko] | ||
Revision as of 08:30, 26 February 2020
Bandai Datach: 32-pin 0.1" card edge (iNES Mapper 157)
**CHR A13 <- | 1 17 | -- +5V
PRG A16 <- | 2 18 | -> ??CHR A12??
PRG A15 <- | 3 19 | -> PRG A17
CPU A12 <- | 4 20 | -> PRG A14
CPU A7 <- | 5 21 | -> CPU A13
CPU A6 <- | 6 22 | -> CPU A8
CPU A5 <- | 7 23 | -> CPU A9
CPU A4 <- | 8 24 | -> CPU A11
CPU A3 <- | 9 25 | -> /ExternalROMRead
CPU A2 <- | 10 26 | -> CPU A10
CPU A1 <- | 11 27 | <> I2C SDA
CPU A0 <- | 12 28 | <> CPU D7
CPU D0 <> | 13 29 | <> CPU D6
CPU D1 <> | 14 30 | <> CPU D5
CPU D2 <> | 15 31 | <> CPU D4
GND -- | 16 32 | <> CPU D3
Notes:
- Pin 1 is used for the external I²C EEPROM clock.
- Pin 18 is Naruko's educated guess
This is almost the standard JEDEC ROM pin order.
Source: Naruko
