User:Zzo38/Mapper 768

I am reserving mapper 768 for my own use.

In all cases, the NES 2.0 file is arranged like (some parts may be omitted, depending on the header):

• Header
• Trainer
• PRG ROM
• CHR ROM
• INST-ROM
• PROM
• 128-byte null-terminated ASCII title
• Extra data for mapper 768 (depending on submapper number)

Submapper 1

Extra data is not used. There is expected to be a file with .nes.v extension (otherwise having the same name), which contains a Verilog code for implementing the mapper.

The first sixty I/O ports of the main module of the Verilog code must correspond to the pins 01 to 60 of the 60-pin Famicom cartridge, in that order. This is followed by the pins for the PRG ROM, CHR ROM, non-battery PRG RAM, non-battery CHR RAM, battery PRG RAM, and battery CHR RAM.

The ROM/RAM pins are only for the ROM/RAM which are existing, and is as follows:

• Chip enable (low to enable)
• Write enable (low to enable; not exist for ROM)
• Address pins (the exact number of pins needed for the ROM/RAM of the size specified in the NES 2.0 header)
• Data pins (always eight)

The commands with $ at front might not be implemented, but should be safely ignored if not implemented. However, if there is a trainer ROM, there will be an additional command $trainer to access 8-bit numbers given the 9-bit address, and $battery_init which tell you if you need to initialize the battery RAM.

Analog commands may be used with the audio signals.