INES Mapper 227: Difference between revisions

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(It's bit 10, value $0400, that reads the solder pad to select the menu. Rewrite the introduction about the CHR-RAM protect part.)
(Rewrite for brevity, correct the solder pad operation (the values x8 are the result of the ROM content at particular locations) and as a template for similar mappers.)
Line 1: Line 1:
[[Category:iNES Mappers|227]][[Category:Multicart mappers|227]]
[[Category:iNES Mappers|227]][[Category:Multicart mappers|227]]
[[INES Mapper 227]] denotes a PRG-ROM+CHR-RAM address-latch-based multicart that is also used for several 1 MiB single-game cartridges from Nanjing, Waixing, and Yancheng. The single-game cartridges lack the CHR-RAM protection facility, yet set the CHR-RAM protect bit, which therefore must be ignored. The variants with and without CHR-RAM protection can be unambiguously separated by the fact that all single-game cartridges using this mapper also mount a battery.
'''iNES Mapper 227''' denotes an address-latch-based multicart circuit board mounting 1 MiB of PRG-ROM plus 8 KiB of unbanked CHR-RAM. A variant used by Chinese RPGs from Nanjing, Waixing (PCB code '''FW-01''') and Yancheng adds 8 KiB battery-backed WRAM.


  Disch's notes, updated:
==Address Latch ($8000-$FFFF, write)==
  Menu information added by Zepper, thanks to zxbdragon. 
  [A~1... .mLQ OQQP PpMS]
  ========================
          ||| |||| |||+-0: PRG A14=p
  =  Mapper 227          =
          ||| |||| |||  1: PRG A14=CPU A14
  ========================
          ||| |||| ||+- 0: Vertical mirroring
 
          ||| |||| ||  1: Horizontal mirroring
 
          ||| |||+-++-- PRG A16..A14 (inner bank)
  Example Game:
          ||+-|++------ PRG A19..A17 (outer bank)
  --------------------------
          ||  +-------- 0: When CPU A14=1: PRG A16..14=LLL
  1200-in-1
          ||            1: When CPU A14=1: PRG A16..14=PPp
  600-in-1
          |+----------- Value for PRG A16..14 when CPU A14=1 and O=0
 
          +------------ 0: PRG A3..A0=CPU A3..A0
 
                        1: PRG A3..A0=Solder pad 3-0
  Notes:
Power-on value: 0
  ---------------------------
  This mapper has 8k CHR-RAM, and also has the ability to write protect its CHR-RAM!
 
 
  Registers:
  ---------------------------
  This mapper uses the address written for its setup. The value is irrelevant.
 
    $8000-FFFF: A~[.... .mLP  OPPP PPMS]
      L = Last PRG Page Mode
      P = PRG Reg
      O = Mode
      M = Mirroring (0=Vert, 1=Horz)
      S = PRG Size
      m = Menu list (see below)
 
  Setup:
  ---------------------------
 
  When 'O' is set, CHR-RAM is write protected (writes have no effect).  'O' also changes the PRG mode.
 
  Note there is funky ANDs and ORs going on below depending on the modes:
 
 
                    $8000  $A000  $C000  $E000 
                  +---------------+---------------+
  O=1, S=0:       |       P      |       P      |
                  +-------------------------------+
   O=1, S=1:       |             < P >            |
                  +-------------------------------+
  O=0, S=0, L=0:  |       P      |   P AND $38  |
                  +---------------+---------------+
  O=0, S=1, L=0:  |   P AND $3E  |   P AND $38  |
                  +---------------+---------------+
  O=0, S=0, L=1:  |       P      |   P OR $07  |
                  +---------------+---------------+
  O=0, S=1, L=1: |  P AND $3E  |  P  OR $07  |
                  +---------------+---------------+


  Menu list:
Effective meaning:
   ---------------------------
Bit 9   Bit 7  Bit 0  Meaning
   The following information does not work for the 1200in1 cartridge!
$200s  $080s   $001s
   Bit 10 of the address written activates the menu list selection. When activated, reading anywhere
   (L)    (O)    (S)
  at $8000-$FFFF returns the menu list type (value x 8) described below; otherwise, returns PRG ROM
  0      0      0    Switchable inner 16 KiB bank PPp at CPU $8000-$BFFF, fixed inner bank #0 at CPU $C000-$FFFF (UNROM-like with fixed bank 0)
  data at $8000-$FFFF.
  0      0       1     Switchable inner 16 KIB bank PP0 at CPU $8000-$BFFF, fixed inner bank #0 at CPU $C000-$FFFF (UNROM-like with only even banks reachable, pointless)
  +-------+----------------------------+
   1       0      0    Switchable inner 16 KiB bank PPp at CPU $8000-$BFFF, fixed inner bank #7 at CPU $C000-$FFFF (UNROM)
  | value | number of selectable games |
   1       0      1     Switchable inner 16 KIB bank PP0 at CPU $8000-$BFFF, fixed inner bank #7 at CPU $C000-$FFFF (UNROM with only even banks reachable, pointless)
  +-------+----------------------------+
   ?      1       0    Switchable 16 KiB inner bank PPp at CPU $8000-$BFFF, mirrored at CPU $C000-$FFFF (NROM-128)
  |  0   | 860 in 1                   |
  ?      1      1    Switchable 32 KiB inner bank PP at CPU $8000-$FFFF (NROM-256)
  |  1  | 460 in 1                  |
  |  2  | 500 in 1                  |
  |  3  | 560 in 1                  |
  |  4  | 600 in 1                  |
  |  5  | 660 in 1                  |
  |  6  | 700 in 1                  |
  |  7  | 860 in 1                  |
  |  8  | 900 in 1                  |
  |  9  | 920 in 1                  |
  |  10  | 940 in 1                  |
  |  11  | 960 in 1                  |
  |  12  | 980 in 1                  |
  |  13  | 400 in 1                  |
  |  14  | 380 in 1                  |
  |  15  | 360 in 1                  |
  +-------+----------------------------+
  | 16~19 | blue screen                |
  | 20    | up to 980, 981+ bugged    |
  | 21    | same of 21                |
  | 22   | 40 in 1, clipped list      |
  | 23~31 | blue screen                |
  | 32   | 420 in 1                   |
  | 33    | 460 in 1 (same of 1) $21  |
  | 34   | 500 in 1 (same of 2) $22  |
  +-------+----------------------------+


The hardware on this board appears to be two [[74157]]s, a [[74153]], two [[74174]]s, a [[7402]], and a [[7432]]. When the 'm' bit is set, one of the 74157s replaces the 4 LSbits of the CPU's address bus with a fixed constant. Evidently, this allowed the pirates to make multiple different seeming multicarts from the same physical ROMs, just by using different PCBs.
* On multicart PCBs (no PRG-RAM/battery), CHR-RAM is write-protected when O=1 and write-enabled when O=0, i.e. write-protected in the NROM-128 and NROM-256 modes.
* When the ''m'' bit is set, PRG A3-A0 are replaced with the values of four solder pads, which when the menu code reads particular ROM locations effectively selects one of up to sixteen menus with different game counts.
* Because all bits are cleared on reset, both CPU $8000-$BFFF and $C000-$FFFF are set to 16 KiB bank #0 on reset.


All bits of the banking register (meaning both 74174s) are most likely cleared on reset.
==Similar mappers==
* [[INES Mapper 242]] is a variant with only up to 512 KiB PRG-ROM that moves the ''m'' bit to a different bit location. A variant with two PRG-ROM chips exists as well.
* [[NES 2.0 Mapper 380]] is an incompatible variant with similar functionality.
* [[NES 2.0 Mapper 449]] is an incompatible variant that adds 32 KiB CHR-RAM bankswitching functionality.


See also: [https://forums.nesdev.org/viewtopic.php?f=9&t=15271 dumping thread]
==See also==
* Dumping thread: https://forums.nesdev.org/viewtopic.php?f=9&t=15271

Revision as of 20:02, 10 November 2021

iNES Mapper 227 denotes an address-latch-based multicart circuit board mounting 1 MiB of PRG-ROM plus 8 KiB of unbanked CHR-RAM. A variant used by Chinese RPGs from Nanjing, Waixing (PCB code FW-01) and Yancheng adds 8 KiB battery-backed WRAM.

Address Latch ($8000-$FFFF, write)

[A~1... .mLQ OQQP PpMS]
         ||| |||| |||+-0: PRG A14=p
         ||| |||| |||  1: PRG A14=CPU A14
         ||| |||| ||+- 0: Vertical mirroring
         ||| |||| ||   1: Horizontal mirroring
         ||| |||+-++-- PRG A16..A14 (inner bank)
         ||+-|++------ PRG A19..A17 (outer bank)
         ||  +-------- 0: When CPU A14=1: PRG A16..14=LLL
         ||            1: When CPU A14=1: PRG A16..14=PPp
         |+----------- Value for PRG A16..14 when CPU A14=1 and O=0
         +------------ 0: PRG A3..A0=CPU A3..A0
                       1: PRG A3..A0=Solder pad 3-0
Power-on value: 0

Effective meaning: 

Bit 9   Bit 7   Bit 0   Meaning
$200s   $080s   $001s
 (L)     (O)     (S)
  0       0       0     Switchable inner 16 KiB bank PPp at CPU $8000-$BFFF, fixed inner bank #0 at CPU $C000-$FFFF (UNROM-like with fixed bank 0)
  0       0       1     Switchable inner 16 KIB bank PP0 at CPU $8000-$BFFF, fixed inner bank #0 at CPU $C000-$FFFF (UNROM-like with only even banks reachable, pointless)
  1       0       0     Switchable inner 16 KiB bank PPp at CPU $8000-$BFFF, fixed inner bank #7 at CPU $C000-$FFFF (UNROM)
  1       0       1     Switchable inner 16 KIB bank PP0 at CPU $8000-$BFFF, fixed inner bank #7 at CPU $C000-$FFFF (UNROM with only even banks reachable, pointless)
  ?       1       0     Switchable 16 KiB inner bank PPp at CPU $8000-$BFFF, mirrored at CPU $C000-$FFFF (NROM-128)
  ?       1       1     Switchable 32 KiB inner bank PP at CPU $8000-$FFFF (NROM-256)
  • On multicart PCBs (no PRG-RAM/battery), CHR-RAM is write-protected when O=1 and write-enabled when O=0, i.e. write-protected in the NROM-128 and NROM-256 modes.
  • When the m bit is set, PRG A3-A0 are replaced with the values of four solder pads, which when the menu code reads particular ROM locations effectively selects one of up to sixteen menus with different game counts.
  • Because all bits are cleared on reset, both CPU $8000-$BFFF and $C000-$FFFF are set to 16 KiB bank #0 on reset.

Similar mappers

  • INES Mapper 242 is a variant with only up to 512 KiB PRG-ROM that moves the m bit to a different bit location. A variant with two PRG-ROM chips exists as well.
  • NES 2.0 Mapper 380 is an incompatible variant with similar functionality.
  • NES 2.0 Mapper 449 is an incompatible variant that adds 32 KiB CHR-RAM bankswitching functionality.

See also

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