Talk:CPU pinout: Difference between revisions
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m (Fiskbit moved page Talk:CPU pin out and signal description to Talk:CPU pinout: Changes page name to fit the format of other pinout pages.) |
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Latest revision as of 05:53, 27 April 2022
Pin 30
The signal from pin 30 goes through the exact same "processing" as the chip's /RESET signal (which includes a Schmitt trigger), at which point it goes to the output logic for the M2 pin (don't know exactly what it does) and then through an inverter which goes to the enables for $4018-$401A and to some other spots (seemingly related to the data buffer used for Sprite DMA). Bit 7 of the writable register at $401A seems to propagate to numerous locations within the sound channels and thus might be responsible for the observation of all writable registers disappearing. --Quietust 16:49, 29 April 2011 (UTC)
- When pin 30's input is "processed" it gets inverted, just like with the /RESET pin (since transistors themselves are active-high) - that signal then gets inverted again (so it's now equal to pin 30's input, normalized) and NORed together with the inverted +RESET signal (so it's also the actual state of the input signal), and that result goes to the M2 pin's output logic; thus, if pin 30 is pulled high, then M2 will not be tri-stated during RESET. --Quietust 20:33, 7 May 2011 (UTC)
- The area where pin 30 goes which I thought was part of the Sprite DMA buffer is actually the logic that controls the R/W pin and the direction of the data pins (it puts the data pins in output mode to handle reading from internal registers), and pulling pin 30 high forces all of $4000-$401F to become internal registers (instead of just $4015). This means that pulling pin 30 high will effectively disable the joypad read ports (but not the write port) - the read enables will still go low, but the CPU won't get any of the data. I'm guessing the designers figured it'd be simpler to do it that way than to combine the 3 read enable signals for $4018-$401A. --Quietust 15:21, 9 May 2011 (UTC)
- Given Lidnariq's edits to the main article, has this actually been tested and verified against actual hardware? --Quietust 19:58, 14 September 2011 (UTC)
- I've just performed a test with my CopyNES (removed the CPU, carefully bent pin 30 up, then plugged it in and clipped a wire between it and VCC) and I can confirm that registers $4018-$401A do behave as described here - reading $4018-$401A returns the output values of each channel, writing $401A bits 0-4 sets the triangle channel position, and setting $401A bit 7 freezes all of the channels. I can also confirm that the joypad ports no longer work, though they still seem to return open bus - presumably, it's actually coming from inside the chip. Additional confirmation would be highly desirable. --Quietust 18:28, 16 September 2011 (UTC)
- Given Lidnariq's edits to the main article, has this actually been tested and verified against actual hardware? --Quietust 19:58, 14 September 2011 (UTC)
- The area where pin 30 goes which I thought was part of the Sprite DMA buffer is actually the logic that controls the R/W pin and the direction of the data pins (it puts the data pins in output mode to handle reading from internal registers), and pulling pin 30 high forces all of $4000-$401F to become internal registers (instead of just $4015). This means that pulling pin 30 high will effectively disable the joypad read ports (but not the write port) - the read enables will still go low, but the CPU won't get any of the data. I'm guessing the designers figured it'd be simpler to do it that way than to combine the 3 read enable signals for $4018-$401A. --Quietust 15:21, 9 May 2011 (UTC)
- Will it work OK if pin 30 and pin 7 are wired together? Is someone able to try this to see what happens? --Zzo38 (talk) 16:24, 1 January 2014 (MST)
Pin 30 is actually used on the Playchoice, in the schematic it is named /SPECIAL. Maybe it is used to disable controller input? Memblers (talk) 04:51, 21 July 2018 (MDT)
M2
M2 goes high 1.5 clock cycles (i.e. three clock edges from the 21.477272MHz master clock) before Φ2, but it goes low at the same time as Φ2.
Would it be okay to still mention the 6502 input clock (Φ0) in conjunction with M2? It helped me a lot when I realized they're "basically" the same (i.e. when reading [1]), and it's pretty easy to miss still scanning through the description. -Ulfalizer (talk) 19:05, 9 April 2013 (MDT)
- I feel like that point belongs with CLK instead of M2; does my last edit satisfy?—Lidnariq (talk) 20:18, 9 April 2013 (MDT)
- Stating that M2 is (roughly) the CPU clock cuts down the chain of inference a bit, and it's handy knowledge even for code monkeys like me when trying to figure out timing diagrams and the like. I'll see if I can come up with some reasonable middle ground. :) -Ulfalizer (talk) 20:24, 9 April 2013 (MDT)
