6502 cycle times: Difference between revisions

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(added blank cells for everything TAX and after)
(make sortable)
 
(2 intermediate revisions by one other user not shown)
Line 1: Line 1:
I put this spreadsheet together because I didn't like the way the timing information was organized in other places.  Some mnemonic/addressing mode combinations do not have an opcode and are marked with "x" because they are not legal instructions.  I may add the illegal opcodes later.  Cells marked with "+" mean add one cycle if a page boundary is crossed.
I put this spreadsheet together because I didn't like the way the timing information was organized in other places.  Some mnemonic/addressing mode combinations do not have an opcode and are left blank because they are not legal instructions.  I may add the illegal opcodes later.  Cells marked with "+" mean add one cycle if a page boundary is crossed.


{| class="wikitable"
{| class="wikitable sortable"
|-
|-
|Mnemonic
!Mnemonic
|Description
!Description
|IMP
!IMP
|IMM
!IMM
|ZP
!ZP
|ZP,X
!ZP,X
|ZP,Y
!ZP,Y
|ABS
!ABS
|ABS,X
!ABS,X
|ABS,Y
!ABS,Y
|IND
!IND
|IND,X
!IND,X
|IND,Y
!IND,Y
|ACC
!ACC
|-
|-
|ADC
|ADC
|ADd with Carry
|ADd with Carry
|x
|
|2
|2
|3
|3
|4
|4
|x
|
|4
|4
|4+
|4+
|4+
|4+
|x
|
|6
|6
|5+
|5+
|x
|
|-
|-
|AND
|AND
|bitwise AND with accumulator
|bitwise AND with accumulator
|x
|
|2
|2
|3
|3
|4
|4
|x
|
|4
|4
|4+
|4+
|4+
|4+
|x
|
|6
|6
|5+
|5+
|x
|
|-
|-
|ASL
|ASL
|Arithmetic Shift Left
|Arithmetic Shift Left
|x
|
|x
|
|5
|5
|6
|6
|x
|
|6
|6
|7
|7
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|BIT
|BIT
|test BITs
|test BITs
|x
|
|x
|
|3
|3
|x
|
|x
|
|4
|4
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|BRK
|BRK
|BreaK
|BreaK
|7
|7
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|CMP
|CMP
|CoMPare accumulator
|CoMPare accumulator
|x
|
|2
|2
|3
|3
|4
|4
|x
|
|4
|4
|4+
|4+
|4+
|4+
|x
|
|6
|6
|5+
|5+
|x
|
|-
|-
|CPX
|CPX
|ComPare X register
|ComPare X register
|x
|
|2
|2
|3
|3
|x
|
|x
|
|4
|4
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|CPY
|CPY
|ComPare Y register
|ComPare Y register
|x
|
|2
|2
|3
|3
|x
|
|x
|
|4
|4
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|DEC
|DEC
|DECrement memory
|DECrement memory
|x
|
|x
|
|5
|5
|6
|6
|x
|
|6
|6
|7
|7
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|EOR
|EOR
|bitwise Exclusive OR
|bitwise Exclusive OR
|x
|
|2
|2
|3
|3
|4
|4
|x
|
|4
|4
|4+
|4+
|4+
|4+
|x
|
|6
|6
|5+
|5+
|x
|
|-
|-
|INC
|INC
|INCrement memory
|INCrement memory
|x
|
|x
|
|5
|5
|6
|6
|x
|
|6
|6
|7
|7
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|JMP
|JMP
|JuMP
|JuMP
|x
|
|x
|
|x
|
|x
|
|x
|
|3
|3
|x
|
|x
|
|5
|5
|x
|
|x
|
|x
|
|-
|-
|JSR
|JSR
|Jump to SubRoutine
|Jump to SubRoutine
|x
|
|x
|
|x
|
|x
|
|x
|
|6
|6
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|LDA
|LDA
|LoaD Accumulator
|LoaD Accumulator
|x
|
|2
|2
|3
|3
|4
|4
|x
|
|4
|4
|4+
|4+
|4+
|4+
|x
|
|6
|6
|5+
|5+
|x
|
|-
|-
|LDX
|LDX
|LoaD X register
|LoaD X register
|x
|
|2
|2
|3
|3
|x
|
|4
|4
|4
|4
|x
|
|4+
|4+
|x
|
|x
|
|x
|
|x
|
|-
|-
|LDY
|LDY
|LoaD Y register
|LoaD Y register
|x
|
|2
|2
|3
|3
|4
|4
|x
|
|4
|4
|4+
|4+
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|LSR
|LSR
|Logical Shift Right
|Logical Shift Right
|x
|
|x
|
|5
|5
|6
|6
|x
|
|6
|6
|7
|7
|x
|
|x
|
|x
|
|x
|
|2
|2
|-
|-
|NOP
|NOP
|No Operation
|No OPeration
|2
|2
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|ORA
|ORA
|bitwise OR with Accumulator
|bitwise OR with Accumulator
|x
|
|2
|2
|3
|3
|4
|4
|x
|
|4
|4
|4+
|4+
|4+
|4+
|x
|
|6
|6
|5+
|5+
|x
|
|-
|-
|ROL
|ROL
|Rotate Left
|Rotate Left
|x
|
|x
|
|5
|5
|6
|6
|x
|
|6
|6
|7
|7
|x
|
|x
|
|x
|
|x
|
|2
|2
|-
|-
|ROR
|ROR
|Rotate Right
|Rotate Right
|x
|
|x
|
|5
|5
|6
|6
|x
|
|6
|6
|7
|7
|x
|
|x
|
|x
|
|x
|
|2
|2
|-
|-
Line 336: Line 336:
|ReTurn from Interrupt
|ReTurn from Interrupt
|6
|6
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|RTS
|RTS
|ReTurn from Subroutine
|ReTurn from Subroutine
|6
|6
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|SBC
|SBC
|SuBtract with Carry
|SuBtract with Carry
|x
|
|2
|2
|3
|3
|4
|4
|x
|
|4
|4
|4+
|4+
|4+
|4+
|x
|
|6
|6
|5+
|5+
|x
|
|-
|-
|STA
|STA
|Store Accumulator
|Store Accumulator
|x
|
|x
|
|3
|3
|4
|4
|x
|
|4
|4
|5
|5
|5
|5
|x
|
|6
|6
|6
|6
|x
|
|-
|-
|STX
|STX
|Store X register
|Store X register
|x
|
|x
|
|3
|3
|x
|
|4
|4
|4
|4
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|STY
|STY
|Store Y register
|Store Y register
|x
|
|x
|
|3
|3
|4
|4
|x
|
|4
|4
|x
|
|x
|
|x
|
|x
|
|x
|
|x
|
|-
|-
|TAX
|TAX

Latest revision as of 18:12, 16 November 2021

I put this spreadsheet together because I didn't like the way the timing information was organized in other places. Some mnemonic/addressing mode combinations do not have an opcode and are left blank because they are not legal instructions. I may add the illegal opcodes later. Cells marked with "+" mean add one cycle if a page boundary is crossed.

Mnemonic Description IMP IMM ZP ZP,X ZP,Y ABS ABS,X ABS,Y IND IND,X IND,Y ACC
ADC ADd with Carry 2 3 4 4 4+ 4+ 6 5+
AND bitwise AND with accumulator 2 3 4 4 4+ 4+ 6 5+
ASL Arithmetic Shift Left 5 6 6 7
BIT test BITs 3 4
BRK BreaK 7
CMP CoMPare accumulator 2 3 4 4 4+ 4+ 6 5+
CPX ComPare X register 2 3 4
CPY ComPare Y register 2 3 4
DEC DECrement memory 5 6 6 7
EOR bitwise Exclusive OR 2 3 4 4 4+ 4+ 6 5+
INC INCrement memory 5 6 6 7
JMP JuMP 3 5
JSR Jump to SubRoutine 6
LDA LoaD Accumulator 2 3 4 4 4+ 4+ 6 5+
LDX LoaD X register 2 3 4 4 4+
LDY LoaD Y register 2 3 4 4 4+
LSR Logical Shift Right 5 6 6 7 2
NOP No OPeration 2
ORA bitwise OR with Accumulator 2 3 4 4 4+ 4+ 6 5+
ROL Rotate Left 5 6 6 7 2
ROR Rotate Right 5 6 6 7 2
RTI ReTurn from Interrupt 6
RTS ReTurn from Subroutine 6
SBC SuBtract with Carry 2 3 4 4 4+ 4+ 6 5+
STA Store Accumulator 3 4 4 5 5 6 6
STX Store X register 3 4 4
STY Store Y register 3 4 4
TAX Transfer A to X 2
TXA Transfer X to A 2
DEX DEcrement X 2
INX INcrement X 2
TAY Transfer A to Y 2
TYA Transfer Y to A 2
DEY Decrement Y 2
INY Increment Y 2
CLC CLear Carry 2
SEC SEt Carry 2
CLI CLear Interrupt 2
SEI SEt Interrupt 2
CLV CLear oVerflow 2
CLD CLear Decimal 2
SED SEt Decimal 2