7402: Difference between revisions

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(Might as well have this)
 
m (→‎Bus Conflict Suppression Implementation: does capital AND make its logical function clearer?)
 
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The '''7402''' (variants 74LS02, 74HC02) is a 74-series logic IC with four independent 2-Input NOR gates.
The '''7402''' (variants 74LS02, 74HC02) is a 74-series logic IC with four independent 2-input NOR gates.
== 74161 Pinout ==
== 7402 Pinout ==
<pre>
        .--\/--.
              .--\/--.
  1Y <- |01  14| -- +5V
        Y1 --|01  14|-- +5V
  1A -> |02  13| -> 4Y
        A1 --|02  13|-- Y4
  1B -> |03  12| <- 4A
        B1 --|03  12|-- B4
  2Y <- |04  11| <- 4B
        Y2 --|04  11|-- A4
  2A -> |05  10| -> 3Y
        A2 --|05  10|-- Y3
  2B -> |06  09| <- 3A
        B2 --|06  09|-- B3
  Gnd -- |07  08| <- 3B
        Gnd --|07  08|-- A3
        `------'
              `------'</pre>
 
== Signal descriptions ==
== Signal descriptions ==
Y is low if either A or B is high, and is high if A and B are both low.
Y is low if either A or B is high, and is high if A and B are both low.


[[Category:7400 series|02]]
== Bus Conflict Suppression Implementation ==
 
74HC02    -- Connection
----------------------------
+5V        -- +5V
02        -- CPU R/W
03        -- CPU R/W
01 (02+03) -- 12 = /(CPU R/W)
11        -- /ROMSEL
12        -- 12
13 (11+12) -- 08, 09 = ROMSEL AND CPU R/W
08        -- 13
09        -- 13
10 (08+09) -- PRG /OE = /(ROMSEL AND CPU R/W)
Others    -- GND
 
This is sometimes used in discrete logic mappers to prevent [[bus conflict]]s (e.g. [[ANROM]]). By combining '''/ROMSEL''' with '''CPU R/W''', the PRG chip can have its output enabled ('''/OE''') only during reads, preventing a conflict with its [[74161|latch]] writes.
 
See: [[Cartridge connector]], [[74161]]
 
[[Category:7400 series|002]]

Latest revision as of 22:58, 14 December 2022

The 7402 (variants 74LS02, 74HC02) is a 74-series logic IC with four independent 2-input NOR gates.

7402 Pinout

        .--\/--.
  1Y <- |01  14| -- +5V
  1A -> |02  13| -> 4Y
  1B -> |03  12| <- 4A
  2Y <- |04  11| <- 4B
  2A -> |05  10| -> 3Y
  2B -> |06  09| <- 3A
 Gnd -- |07  08| <- 3B
        `------'

Signal descriptions

Y is low if either A or B is high, and is high if A and B are both low.

Bus Conflict Suppression Implementation

74HC02     -- Connection
----------------------------
+5V        -- +5V
02         -- CPU R/W
03         -- CPU R/W
01 (02+03) -- 12 = /(CPU R/W)
11         -- /ROMSEL
12         -- 12
13 (11+12) -- 08, 09 = ROMSEL AND CPU R/W
08         -- 13
09         -- 13
10 (08+09) -- PRG /OE = /(ROMSEL AND CPU R/W)
Others     -- GND

This is sometimes used in discrete logic mappers to prevent bus conflicts (e.g. ANROM). By combining /ROMSEL with CPU R/W, the PRG chip can have its output enabled (/OE) only during reads, preventing a conflict with its latch writes.

See: Cartridge connector, 74161