APU: Difference between revisions

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m (the Visual 2A03 just took existing images (produced using whatever expensive methods) and processed them by hand - the only cost was my own time, and I'd like to think it was worth it...)
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The NES APU is the audio processing unit in the NES console which generates sound for games. It is implemented in the RP2A03 (NTSC) and RP2A07 (PAL) chips. Its [[APU registers|registers]] are mapped in the range $4000-$4017.
The NES APU is the audio processing unit in the NES console which generates sound for games. It is implemented in the RP2A03 (NTSC) and RP2A07 (PAL) chips. Its [[APU registers|registers]] are mapped in the range $4000-$4017.


For clarity, this reference describes the ''abstract'' operation of the APU, ''not the exact hardware implementation''. As long as the behavior is documented, the exact kind of counter or shift register used to implement a particular behavior is essentially irrelevant; in any case, the exact hardware implementation can only be speculated on without access to very expensive chip-level reverse-engineering tools (though expense hasn't stopped the [http://www.qmtpro.com/~nes/chipimages/visual2a03/ Visual 2A03] project from doing just this).
For clarity, this reference describes the ''abstract'' operation of the APU, ''not the exact hardware implementation''. As long as the behavior is documented, the exact kind of counter or shift register used to implement a particular behavior is essentially irrelevant; the exact hardware implementation can be determined by examining close-up images of the die itself (as was done with the [http://www.qmtpro.com/~nes/chipimages/visual2a03/ Visual 2A03] project).


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Revision as of 17:38, 12 March 2012

The NES APU is the audio processing unit in the NES console which generates sound for games. It is implemented in the RP2A03 (NTSC) and RP2A07 (PAL) chips. Its registers are mapped in the range $4000-$4017.

For clarity, this reference describes the abstract operation of the APU, not the exact hardware implementation. As long as the behavior is documented, the exact kind of counter or shift register used to implement a particular behavior is essentially irrelevant; the exact hardware implementation can be determined by examining close-up images of the die itself (as was done with the Visual 2A03 project).

Registers Channel Units
$4000-$4003 Pulse 1 Timer, Length Counter, Envelope, Sweep
$4004-$4007 Pulse 2 Timer, Length Counter, Envelope, Sweep
$4008-$400B Triangle Timer, Length Counter, linear counter
$400C-$400F Noise Timer, Length Counter, Envelope, shift register w/ feedback
$4010-$4013 DMC Timer, memory reader, sample buffer, output unit
$4015 All Length Counter enable and status
$4017 All Frame Counter/Sequencer

Each channel has a variable-rate timer clocking a waveform generator, and various modulators driven by low-frequency clocks from the Frame Counter/Sequencer. The DMC plays samples while the other channels play waveforms. Each sub-unit of a channel generally runs independently and in parallel to other units, and modification of a channel's parameter usually affects only one sub-unit and doesn't take effect until that unit's next internal cycle begins.

The read/write status register allows channels to be enabled and disabled, and their current length counter status to be queried.

The outputs from all the channels are combined using a non-linear mixing scheme.

On board extra audio register reference

Note