APU Frame Counter: Revision history

2 July 2022

• curprev 18:0018:00, 2 July 2022‎ Quietust talk contribs‎ m 4,484 bytes +16‎ No edit summary
• curprev 06:3206:32, 2 July 2022‎ Egor talk contribs‎ 4,468 bytes +135‎ split NTSC and PAL cycle counts into different columns

26 February 2022

• curprev 22:2022:20, 26 February 2022‎ Lidnariq talk contribs‎ m 4,333 bytes +1‎ →‎Mode 0: 4-Step Sequence (bit 7 of $4017 clear): typo
• curprev 20:3720:37, 26 February 2022‎ Quietust talk contribs‎ 4,332 bytes +553‎ Add PAL timings, extracted from RP2A07 chip images

27 December 2016

• curprev 12:3912:39, 27 December 2016‎ Zepper talk contribs‎ m 3,779 bytes −178‎ Removed duplicated/unnecessary note.

22 February 2015

• curprev 19:3919:39, 22 February 2015‎ Dwedit talk contribs‎ 3,957 bytes +53‎ →‎Mode 0: 4-Step Sequence (bit 7 of $4017 clear)

15 August 2013

• curprev 09:0409:04, 15 August 2013‎ Ulfalizer talk contribs‎ 3,904 bytes +45‎ The write delay was off by one CPU cycle too. Perhaps that compensated. (Derived from Visual 2A03.)
• curprev 08:3808:38, 15 August 2013‎ Ulfalizer talk contribs‎ 3,859 bytes +99‎ The quarter and half frame signals are generated with a delay of one CPU cycle (see talk page)

13 June 2013

• curprev 15:5615:56, 13 June 2013‎ Ulfalizer talk contribs‎ 3,760 bytes +9‎ Also specify reg
• curprev 15:5515:55, 13 June 2013‎ Ulfalizer talk contribs‎ 3,751 bytes +234‎ Add overview for the frame interrupt flag

27 May 2012

• curprev 04:0604:06, 27 May 2012‎ Drag talk contribs‎ m 3,517 bytes +4‎ →‎Mode 1: 5-Step Sequence (bit 7 of $4017 set): line breaks. grrrrr
• curprev 04:0604:06, 27 May 2012‎ Drag talk contribs‎ m 3,513 bytes +178‎ →‎Mode 1: 5-Step Sequence (bit 7 of $4017 set): repeating the information about the immediate clock generated from writing to $4017 with bit 7 set.

26 May 2012

• curprev 22:5522:55, 26 May 2012‎ Rainwarrior talk contribs‎ m 3,335 bytes +27‎ clarify synonym
• curprev 20:0120:01, 26 May 2012‎ Rainwarrior talk contribs‎ m 3,308 bytes +17‎ APU category

13 July 2011

• curprev 03:5703:57, 13 July 2011‎ Zepper talk contribs‎ m 3,291 bytes +4‎ No edit summary
• curprev 03:3603:36, 13 July 2011‎ Quietust talk contribs‎ m 3,287 bytes −2‎ No edit summary
• curprev 03:1603:16, 13 July 2011‎ Quietust talk contribs‎ 3,289 bytes 0‎ make them actually APU cycles...
• curprev 03:1403:14, 13 July 2011‎ Quietust talk contribs‎ 3,289 bytes −17‎ it takes 2 CPU cycles (1 APU cycle) to reset, not 2 APU cycles
• curprev 01:1801:18, 13 July 2011‎ Drag talk contribs‎ m 3,306 bytes −52‎ I guess it isn't quite the "next" APU cycle
• curprev 01:1601:16, 13 July 2011‎ Drag talk contribs‎ 3,358 bytes +539‎ Adding some timing explanations, hopefully I've interpreted these correctly

10 July 2011

• curprev 21:1421:14, 10 July 2011‎ Quietust talk contribs‎ 2,819 bytes −237‎ there is NO 240Hz divider - the frame counter is a 15-bit counter (LFSR) that generates triggers at each cycle count; also, subtract 3 from cycle counts because of the reload delay on $4017 write

9 July 2011

• curprev 02:2802:28, 9 July 2011‎ Zepper talk contribs‎ m 3,056 bytes +7‎ →‎Mode 1: 5-Step Sequence ($4017 : $80)
• curprev 02:2802:28, 9 July 2011‎ Zepper talk contribs‎ m 3,049 bytes +23‎ →‎Mode 0: 4-Step Sequence
• curprev 02:2702:27, 9 July 2011‎ Zepper talk contribs‎ 3,026 bytes +101‎ →‎Mode 1: 5-Step Sequence: added APU cycles, plus $4017 bit
• curprev 02:2302:23, 9 July 2011‎ Zepper talk contribs‎ 2,925 bytes +224‎ →‎Mode 0: 4-Step Sequence: added APU cycles, plus frameIRQ triplet.

2 April 2010

• curprev 23:5323:53, 2 April 2010‎ Zepper talk contribs‎ m 2,701 bytes −3‎ →‎you forgot one table :)
• curprev 21:4221:42, 2 April 2010‎ Tepples talk contribs‎ m 2,704 bytes +10‎ →‎Mode 0: 4-Step Sequence: more specific
• curprev 21:4221:42, 2 April 2010‎ Tepples talk contribs‎ 2,694 bytes +453‎ possible purpose

23 February 2010

• curprev 16:4216:42, 23 February 2010‎ Tepples talk contribs‎ 2,241 bytes +25‎ ...so misleading I made the same mistake.
• curprev 11:5611:56, 23 February 2010‎ Tepples talk contribs‎ 2,216 bytes +109‎ Possibly misleading name

12 June 2009

• curprev 15:1015:10, 12 June 2009‎ Banshaku talk contribs‎ m 2,107 bytes −4‎ No edit summary
• curprev 15:1015:10, 12 June 2009‎ Banshaku talk contribs‎ m 2,111 bytes +2,111‎ Created page with 'The NES APU frame counter generates low-frequency clocks for the channels and an optional 60 Hz interrupt. The frame counter contains the following: divider...'