APU Frame Counter

The NES APU frame counter (or frame sequencer) generates low-frequency clocks for the channels and an optional 60 Hz interrupt. The name "frame counter" might be slightly misleading because the clocks have nothing to do with the video signal.

The frame counter contains the following: divider, looping clock sequencer, frame interrupt flag.

The sequencer is clocked on every other CPU cycle, so 2 CPU cycles = 1 APU cycle. The sequencer keeps track of how many APU cycles have elapsed in total, and each step of the sequence will occur once that total has reached the indicated amount. Once the last step has executed, the count resets to 0 on the next APU cycle.

Address	Bitfield	Description
$4017	MI--.----	Set mode and interrupt (write)
Bit 7	M--- ----	Sequencer mode: 0 selects 4-step sequence, 1 selects 5-step sequence
Bit 6	-I-- ----	Interrupt inhibit flag. If set, the frame interrupt flag is cleared, otherwise it is unaffected.
Side effects		After 2 or 3 CPU clock cycles*, the timer is reset. If the mode flag is set, then both "quarter frame" and "half frame" signals are also generated.

* If the write occurs during an APU cycle, the effects occur 2 CPU cycles later, and if the write occurs between APU cycles, the effects occur 3 CPU cycles later.

TODO: describe PAL

The frame interrupt flag is connected to the CPU's IRQ line. It is set at a particular point in the 4-step sequence (see below) provided the interrupt inhibit flag in $4017 is clear, and can be cleared either by reading $4015 (which also returns its old status) or by setting the interrupt inhibit flag.

Mode 0: 4-Step Sequence (bit 7 of $4017 clear)

Step	APU cycles	Envelopes & triangle's linear counter (Quarter frame)	Length counters & sweep units (Half frame)	Frame interrupt flag
1	3728	Clock
2	7456	Clock	Clock
3	11185	Clock
4	14914	Clock	Clock	Set if interrupt inhibit is clear
	14914.5			Set if interrupt inhibit is clear
	0 (14915)			Set if interrupt inhibit is clear
		240 Hz (approx.)	120 Hz (approx.)	60 Hz (approx.)

In this mode, the interrupt flag is set every 29830 CPU cycles, which is slightly slower than the 29780.5 CPU cycles per NTSC PPU frame.

Some Nintendo arcade boards, even those not directly based on the NES, use the 2A03 CPU as a sound processor. One of these is Punch-Out!!. This IRQ allows the CPU to keep time even if no PPU is connected to the bus.

Mode 1: 5-Step Sequence (bit 7 of $4017 set)

Step	APU cycles	Envelopes & triangle's linear counter (Quarter frame)	Length counters & sweep units (Half frame)
1	3728	Clock
2	7456	Clock	Clock
3	11185	Clock
4	14914
5	18640	Clock	Clock
	0 (18641)
		192 Hz (approx.), uneven timing	96 Hz (approx.), uneven timing

In this mode, the frame interrupt flag is never set.
Note: Writing to $4017 with bit 7 set will immediately generate a clock for both the quarter frame and the half frame units, regardless of what the sequencer is doing.