APU Noise: Difference between revisions
m (This NOISE shift register is only 15 bits, not 16. So I removed the "-" that was representing the 16th bit to avoid any confusion. Now it is "%E------.-6----10") |
(Corrected LFSR description and clarified width) |
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When the timer clocks the shift register, the following two actions occur in order: | When the timer clocks the shift register, the following two actions occur in order: | ||
# Bit | # Bit 15 of the shift register is set to the exclusive-OR of bit 0 and one other bit: bit 6 if loop is set, otherwise bit 1.<br>Shift register bits: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 | ||
# The shift register is shifted one bit right (bit 0 is lost). | # The shift register is shifted one bit right (bit 0 is lost). | ||
This results in a pseudo-random bit sequence, 32767 bits long when loop is clear, otherwise 93 bits long (the particular 93-bit sequence depends on where in the 32767-bit sequence the shift register was when loop was set). | This results in a pseudo-random bit sequence, 32767 bits long when loop is clear, otherwise 93 bits long (the particular 93-bit sequence depends on where in the 32767-bit sequence the shift register was when loop was set). Note that the shift register only needs to be 15 bits wide normally. The extra bit 15 above simplifies the description of clocking. | ||
The [[APU Mixer|mixer]] receives the current [[APU Envelope|envelope volume]] except when | The [[APU Mixer|mixer]] receives the current [[APU Envelope|envelope volume]] except when | ||
Revision as of 04:37, 22 February 2010
The NES APU noise channel generates pseudo-random 1-bit noise at 16 different frequencies.
The noise channel contains the following: envelope generator, timer, shift register with feedback, length counter.
Timer --> Shift Register Length Counter
| |
v v
Envelope -------> Gate ----------> Gate --> (to mixer)
| $400C | --le.eeee | Length counter halt and envelope (write) |
| $400E | L---.PPPP | Loop and period (write) |
| bit 7 | L--- ---- | Loop flag |
| bits 3-0 | ---- PPPP | The timer period is set to entry P of the following:Rate $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F
--------------------------------------------------------------------------
NTSC 4, 8, 16, 32, 64, 96, 128, 160, 202, 254, 380, 508, 762, 1016, 2034, 4068
PAL 4, 7, 14, 30, 60, 88, 118, 148, 188, 236, 354, 472, 708, 944, 1890, 3778
|
| $400F | llll.l--- | Length counter load and envelope restart (write) |
When the timer clocks the shift register, the following two actions occur in order:
- Bit 15 of the shift register is set to the exclusive-OR of bit 0 and one other bit: bit 6 if loop is set, otherwise bit 1.
Shift register bits: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - The shift register is shifted one bit right (bit 0 is lost).
This results in a pseudo-random bit sequence, 32767 bits long when loop is clear, otherwise 93 bits long (the particular 93-bit sequence depends on where in the 32767-bit sequence the shift register was when loop was set). Note that the shift register only needs to be 15 bits wide normally. The extra bit 15 above simplifies the description of clocking.
The mixer receives the current envelope volume except when
- Bit 0 of the shift register is set, or
- The length counter is zero
On power-up, the shift register is loaded with the value 1.
