APU Noise: Difference between revisions
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| '''$400E''' || <tt> | | '''$400E''' || <tt>M---.PPPP</tt> || '''Mode and period''' (write) | ||
|- | |- | ||
| bit 7 || <tt> | | bit 7 || <tt>M--- ----</tt> || Mode flag | ||
|- | |- | ||
| bits 3-0 || <tt>---- PPPP</tt> || The timer period is set to entry P of the following:<br> | | bits 3-0 || <tt>---- PPPP</tt> || The timer period is set to entry P of the following:<br> | ||
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When the timer clocks the shift register, the following actions occur in order: | When the timer clocks the shift register, the following actions occur in order: | ||
# Feedback is calculated as the exclusive-OR of bit 0 and one other bit: bit 6 if | # Feedback is calculated as the exclusive-OR of bit 0 and one other bit: bit 6 if Mode flag is set, otherwise bit 1. | ||
# The shift register is shifted right by one bit. | # The shift register is shifted right by one bit. | ||
# Bit 14, the leftmost bit, is set to the feedback calculated earlier. | # Bit 14, the leftmost bit, is set to the feedback calculated earlier. | ||
This results in a pseudo-random bit sequence, 32767 bits long when | This results in a pseudo-random bit sequence, 32767 bits long when Mode flag is clear, otherwise 93 bits long (the particular 93-bit sequence depends on where in the 32767-bit sequence the shift register was when Mode flag was set). | ||
The [[APU Mixer|mixer]] receives the current [[APU Envelope|envelope volume]] except when | The [[APU Mixer|mixer]] receives the current [[APU Envelope|envelope volume]] except when | ||
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On power-up, the shift register is loaded with the value 1. | On power-up, the shift register is loaded with the value 1. | ||
The earliest revisions of the 2A03 CPU ignored the | The earliest revisions of the 2A03 CPU ignored the Mode flag, treating it as always 0. These CPUs were used in the first batch of Famicom consoles that were recalled, in Vs. System boards, and in the arcade games that used the 2A03 as a sound coprocessor.[http://nesdev.parodius.com/bbs/viewtopic.php?p=58046#58046] | ||
Revision as of 10:00, 30 December 2010
The NES APU noise channel generates pseudo-random 1-bit noise at 16 different frequencies.
The noise channel contains the following: envelope generator, timer, shift register with feedback, length counter.
Timer --> Shift Register Length Counter
| |
v v
Envelope -------> Gate ----------> Gate --> (to mixer)
| $400C | --le.eeee | Length counter halt and envelope (write) |
| $400E | M---.PPPP | Mode and period (write) |
| bit 7 | M--- ---- | Mode flag |
| bits 3-0 | ---- PPPP | The timer period is set to entry P of the following:Rate $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B $C $D $E $F
--------------------------------------------------------------------------
NTSC 4, 8, 16, 32, 64, 96, 128, 160, 202, 254, 380, 508, 762, 1016, 2034, 4068
PAL 4, 7, 14, 30, 60, 88, 118, 148, 188, 236, 354, 472, 708, 944, 1890, 3778
|
| $400F | llll.l--- | Length counter load and envelope restart (write) |
The shift register is 15 bits wide, with bits numbered
14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0
When the timer clocks the shift register, the following actions occur in order:
- Feedback is calculated as the exclusive-OR of bit 0 and one other bit: bit 6 if Mode flag is set, otherwise bit 1.
- The shift register is shifted right by one bit.
- Bit 14, the leftmost bit, is set to the feedback calculated earlier.
This results in a pseudo-random bit sequence, 32767 bits long when Mode flag is clear, otherwise 93 bits long (the particular 93-bit sequence depends on where in the 32767-bit sequence the shift register was when Mode flag was set).
The mixer receives the current envelope volume except when
- Bit 0 of the shift register is set, or
- The length counter is zero
On power-up, the shift register is loaded with the value 1.
The earliest revisions of the 2A03 CPU ignored the Mode flag, treating it as always 0. These CPUs were used in the first batch of Famicom consoles that were recalled, in Vs. System boards, and in the arcade games that used the 2A03 as a sound coprocessor.[1]
