Bandai LZ93D50 pinout

Bandai LZ93D50: 52-pin shrink PDIP (Canonically iNES Mapper 159)

           .---\/---.
        ?? |  1  52 | -- +5V
        ?? |  2  51 | -> WRAM /CS
PRG /CE <- |  3  50 | ?? ?
    +5V ?? |  4  49 | ?? +5V
     M2 -> |  5  48 | ?? ?
CPU A13 -> |  6  47 | -> PRG A17
CPU A14 -> |  7  46 | -> PRG A15
 CPU A3 -> |  8  45 | -> PRG A14
 CPU A2 -> |  9  44 | -> PRG A16
 CPU A1 -> | 10  43 | <- CPU D7
 CPU A0 -> | 11  42 | <- CPU D6
/ROMSEL -> | 12  41 | <- CPU D5
 CPU D0 -> | 13  40 | <> CPU D4
 CPU D1 -> | 14  39 | <- CPU D3
 CPU D2 -> | 15  38 | -> CPU IRQ#
    R/W -> | 16  37 | -> VRAM A10
PPU /RD -> | 17  36 | -> CHR A17
CHR A15 <- | 18  35 | -> CHR A14
CHR A12 <- | 19  34 | -> CHR A13
PPU A10 -> | 20  33 | -> CHR A11
PPU A11 -> | 21  32 | -> CHR A16
PPU A12 -> | 22  31 | -> CHR A10
PPU A13 -> | 23  30 | -> CHR /CE
    GND -- | 24  29 | <- I2C read enable
      ? ?? | 25  28 | -> I²C SCL
    GND -- | 26  27 | <> I²C SDA
           '--------'

Bandai's variants of the LZ93D50 are almost as bad as MMC1.

BA-JUMP2: supports PRG RAM instead of I²C, and increase PRG max to 512KiB:

PPU /RD -> | 17  36 | -> n/c
    n/c <- | 18  35 | -> n/c
    n/c <- | 19  34 | -> n/c
PPU A10 -> | 20  33 | -> n/c
PPU A11 -> | 21  32 | -> n/c
    GND -> | 22  31 | -> PRG A18
    GND -> | 23  30 | -> CHR /CE
    GND -- | 24  29 | <- GND
      ? ?? | 25  28 | -> PRG RAM +CE
    GND -- | 26  27 | <> n/c
           '--------'

Datach Joint ROM System: Two separate I²C clocks, and external barcode reader.

This IC is actually a 52-pin QFP, with a slightly different pin order from the PDIP instantiation. The pertinent changes:

• I²C SCL is only for the internal EEPROM
• CHR A10 is External I²C SCL
• WRAM /CS drives a tristateable buffer that connects barcode data to CPU D3.

Naruko says PPU A12 is connected to LZ93D50P, so it's not clear why one has to write I²C clock data to only $8000 through $8003, rather than all eight ports.