CPU pinout: Difference between revisions
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(Make the M2/φ0 connection explicit. (It can be inferred, but I think I would have missed it, so putting it in.)) |
(Add duty cycle information for M2) |
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* /NMI and /IRQ are the two interrupt pins. See the 6502 manual for more detailed explanation. | * /NMI and /IRQ are the two interrupt pins. See the 6502 manual for more detailed explanation. | ||
* M2 can be considered as a "signals ready" pin. It is a modified version the 6502's φ2 (which roughly corresponds to the CPU input clock φ0) that allows for slower ROMs. | * M2 can be considered as a "signals ready" pin. It is a modified version the 6502's φ2 (which roughly corresponds to the CPU input clock φ0) that allows for slower ROMs. | ||
** M2 has a duty cycle (fraction of a cycle the signal stays high) of 5/8 or 62.5%. Equivalently, a CPU read (which happens during the second, high phase of M2) takes 1.875 PPU cycles. The internal φ2 duty cycle is closer to 50%. | |||
* TST (tentative name) (pin 30) is special: normally it is grounded in the NES, Famicom, PC10/VS. NES and other Nintendo Arcade Boards (Popeye and Donkey Kong 3). But if it is pulled high, extra diagnostic registers to test the sound hardware are enabled from $4018 through $401A, and the joystick ports $4016 and $4017 become open bus. | * TST (tentative name) (pin 30) is special: normally it is grounded in the NES, Famicom, PC10/VS. NES and other Nintendo Arcade Boards (Popeye and Donkey Kong 3). But if it is pulled high, extra diagnostic registers to test the sound hardware are enabled from $4018 through $401A, and the joystick ports $4016 and $4017 become open bus. | ||
Revision as of 05:48, 14 April 2013
Pin out
.--\/--.
AD1 <- |01 40| -- +5V
AD2 <- |02 39| -> OUT0
/RST -> |03 38| -> OUT1
A00 <- |04 37| -> OUT2
A01 <- |05 36| -> /OE1
A02 <- |06 35| -> /OE2
A03 <- |07 34| -> R/W
A04 <- |08 33| <- /NMI
A05 <- |09 32| <- /IRQ
A06 <- |10 31| -> M2
A07 <- |11 30| <- TST (usually GND)
A08 <- |12 29| <- CLK
A09 <- |13 28| <> D0
A10 <- |14 27| <> D1
A11 <- |15 26| <> D2
A12 <- |16 25| <> D3
A13 <- |17 24| <> D4
A14 <- |18 23| <> D5
A15 <- |19 22| <> D6
GND -- |20 21| <> D7
`------'
Signal description
Active-Low signals are indicated by a "/".
- CLK is the 21.47727 MHz (NTSC) or 26.6017 MHz (PAL) clock input. Internally, this clock is divided by 12 (NTSC 2A03) or 16 (PAL 2A07) to feed the 6502's clock input φ0. (φ0 is in turn inverted to form φ1, which is then inverted to form φ2.)
- AD1 (both pulse waves) and AD2 (triangle, noise, and DPCM) are the Audio Out pins.
- Axx is the address bus and Dx the data bus.
- OUT0-OUT2 are output pins used by the controllers ($4016 output latch bits 0-2). These 3 pins are connected to either the NES's or Famicom's expansion port, and OUT0 is additionally used as the "strobe" signal (OUT) on both controller ports.
- /OE1 and /OE2 also go to the controller ports, and each enable the output of their respective controller, if present.
- R/W is the read/write signal, which is used to indicate operations of the same names. Low is write.
- /NMI and /IRQ are the two interrupt pins. See the 6502 manual for more detailed explanation.
- M2 can be considered as a "signals ready" pin. It is a modified version the 6502's φ2 (which roughly corresponds to the CPU input clock φ0) that allows for slower ROMs.
- M2 has a duty cycle (fraction of a cycle the signal stays high) of 5/8 or 62.5%. Equivalently, a CPU read (which happens during the second, high phase of M2) takes 1.875 PPU cycles. The internal φ2 duty cycle is closer to 50%.
- TST (tentative name) (pin 30) is special: normally it is grounded in the NES, Famicom, PC10/VS. NES and other Nintendo Arcade Boards (Popeye and Donkey Kong 3). But if it is pulled high, extra diagnostic registers to test the sound hardware are enabled from $4018 through $401A, and the joystick ports $4016 and $4017 become open bus.
