CPU variants: Difference between revisions

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(Fiskbit PM'd me about the UM6561AF-2)
(add 2A03/2A07 duty cycles)
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{| class="tabular"
{| class="tabular"
| RP2A03 || M2 duty cycle is 3/4 instead of 5/8. Lacks tonal noise mode. Has broken and disabled programmable interval timer on-die. Other differences?
| RP2A03 || M2 duty cycle is 17/24 instead of 15/24 [https://forums.nesdev.org/viewtopic.php?p=166761#p166761]. Lacks tonal noise mode. Has broken and disabled programmable interval timer on-die. Other differences?
|-
|-
| RP2A03E || no known differences
| RP2A03E || no known differences
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| RP2A04 || Not actually a CPU at all, just a jumper in a 40-pin PDIP
| RP2A04 || Not actually a CPU at all, just a jumper in a 40-pin PDIP
|-
|-
| RP2A07 || input clock divider is 16. Changes to noise, DPCM, frame timer tables. Fixed DPCM RDY address bus glitches. Other differences?
| RP2A07 || input clock divider is 16. M2 duty cycle is 19/32 [https://forums.nesdev.org/viewtopic.php?p=166761#p166761]. Changes to noise, DPCM, frame timer tables. Fixed DPCM RDY address bus glitches. Other differences?
|-
|-
| RP2A07A || no known differences relative to 2A07letterless
| RP2A07A || no known differences relative to 2A07letterless

Revision as of 17:56, 1 October 2020

Beyond the well-studied 2A03G, we know of the following CPU revisions, both made by Ricoh and other manufacturers:

RP2A03 M2 duty cycle is 17/24 instead of 15/24 [1]. Lacks tonal noise mode. Has broken and disabled programmable interval timer on-die. Other differences?
RP2A03E no known differences
RP2A03G reference model
RP2A03H no known differences
RP2A04 Not actually a CPU at all, just a jumper in a 40-pin PDIP
RP2A07 input clock divider is 16. M2 duty cycle is 19/32 [2]. Changes to noise, DPCM, frame timer tables. Fixed DPCM RDY address bus glitches. Other differences?
RP2A07A no known differences relative to 2A07letterless
MG-P-501 Micro Genius-made clone. No specifics known.
UA6527 UMC-made clone of 2A03G. Has swapped pulse channel duty cycles.
UA6527P UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. input clock divider is 15. Otherwise believed same as 6527.

Two revisions exist: before mid-1990 (which has UMC logo on left) and after-mid-1990 (which has UMC logo on top). It is said that old UMC CPU has broken DMC reader function [3]. Addidionally it has input clock divider equals to 16 in contrary to the 15 present in newer one, that would explain why some games work differently (for example: CodeMasters' titles)

Ua6527p old.png Ua6527p new.png

UA6540 UMC-made clone of 2A07 [4]. Has swapped pulse duty cycles.
UM6557 Believed to be a 100% duplicate of UA6527, for use in SECAM regions.
UM6561xx-1 NES-on-a-chip for NTSC. Revisions "xx" AF, BF, CF, F known. Earlier revisions (which?) CPU half believed identical to UA6527; later revisions correct pulse channel duties.
UM6561xx-2 NES-on-a-chip for PAL-B. Revisions "xx" AF, BF, CF, F known. Earlier revisions (which?) CPU half believed identical to UA6527P; later revisions correct pulse channel duties.

"AF" revision pulse wave duties observed to be same as 2A03.

T1818 ??-made NES-on-a-chip, NTSC timing. Believed to exist, but evidence currently scant.
T1818P ??-made NES-on-a-chip[[5]. Requires external 2 KiB RAMs for CPU and PPU. Swapped pulse duty cycles.
TA-03N ??-made clone of 2A03G
TA-03NP ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15.
TA-03NP1 ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems?
PM03 Gradiente-made clone of 2A03G. [6]

If you know of other differences or other revisions, please add them!

See also