CPU variants: Difference between revisions

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(Notes that DMC status bit is cleared 1 APU cycle late on UA6527P, TA-03NP1, (T)1818P, UM6561-2. Other clones untested.)
(eugene S in the discord described pulse duties for these two)
Line 31: Line 31:
[[File:CPU=UA6527-8909-BS.jpg|400px]] [[File:CPU=UA6527-9310-CG-C12520.jpg|400px]]
[[File:CPU=UA6527-8909-BS.jpg|400px]] [[File:CPU=UA6527-9310-CG-C12520.jpg|400px]]
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| UA6527P || UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. input clock divider is 15. Otherwise believed same as 6527.
| UA6527P || UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. input clock divider is 15. Still has swapped pulse channel duty cycles. Otherwise believed same as 6527.
Two revisions exist: before mid-1990 (which has UMC logo on left) and after-mid-1990 (which has UMC logo on top). It is said that old UMC CPU has broken DMC reader function [https://forums.nesdev.org/viewtopic.php?t=13024&p=151220].
Two revisions exist: before mid-1990 (which has UMC logo on left) and after-mid-1990 (which has UMC logo on top). It is said that old UMC CPU has broken DMC reader function [https://forums.nesdev.org/viewtopic.php?t=13024&p=151220].
Additionally it has input clock divider equals to 16 in contrary to the 15 present in newer one, that would explain why some games work differently (for example: CodeMasters' titles)
Additionally it has input clock divider equals to 16 in contrary to the 15 present in newer one, that would explain why some games work differently (for example: CodeMasters' titles)
Line 74: Line 74:
[[File:CPU=TA-03NP EWP0124.jpg|400px]] But not this one, this input clock divider is 12.
[[File:CPU=TA-03NP EWP0124.jpg|400px]] But not this one, this input clock divider is 12.
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| TA-03NP1 || ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.
| TA-03NP1 || ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? Correct pulse channel duties. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.
[[File:CPU=TA-03NP1 6527P 9231.jpg|400px]]
[[File:CPU=TA-03NP1 6527P 9231.jpg|400px]]
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Revision as of 01:40, 26 February 2023

Beyond the well-studied 2A03G, we know of the following CPU revisions, both made by Ricoh and other manufacturers:

RP2A03 M2 duty cycle is 17/24 instead of 15/24 [1]. Lacks tonal noise mode. APU Frame Counter not restarted on reset. Has broken and disabled programmable interval timer on-die. Pin 30 connects to nothing. Other differences?

CPU=RP2A03 3M294.jpg CPU=RP2A03 3L4 27.jpg

RP2A03E Pin 30 may connect to 6502 /RDY input.

CPU=RP2A03E 5K5 26.jpg CPU=RP2A03E VF4109 5H4 8582.jpg

RP2A03G Reference model. Pin 30 enables a CPU test mode. Later runs introduced a DMC DMA bug [2].

CPU=RP2A03G 8K5 81.jpg

RP2A03H No known differences from late RP2A03G.

CPU=RP2A03H 4AM 4F.jpg

RP2A04 Not actually a CPU at all, just a jumper in a 40-pin PDIP

CPU=RP2A04 2J 6C2 01.jpg

RP2A07 Input clock divider is 16. M2 duty cycle is 19/32 [3]. Changes to noise, DPCM, frame timer tables. Fixed DPCM RDY address bus glitches. Pin 30 connects to 6502 /RDY input.

CPU=RP2A07 7C4 39.jpg CPU=RP2A07 8F3 78.jpg

RP2A07A no known differences relative to 2A07letterless

CPU=RP2A07A 1GM 36.jpg CPU=RP2A07A 2JM 3L.jpg

MG-N-501 CPU=MG-N-501 8933.jpg Unlike early UA6527, DMC works
MG-P-501 Micro Genius-made clone. Die has the same (UMC) © Ⓜ B6167F marking as a UA6527P.

CPU=MG-P-501 9221S 415521.jpg

UA6527 UMC-made clone of 2A03G. Has swapped pulse channel duty cycles.

CPU=UA6527-8909-BS.jpg CPU=UA6527-9310-CG-C12520.jpg

UA6527P UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. input clock divider is 15. Still has swapped pulse channel duty cycles. Otherwise believed same as 6527.

Two revisions exist: before mid-1990 (which has UMC logo on left) and after-mid-1990 (which has UMC logo on top). It is said that old UMC CPU has broken DMC reader function [4]. Additionally it has input clock divider equals to 16 in contrary to the 15 present in newer one, that would explain why some games work differently (for example: CodeMasters' titles)

One revision has (UMC) © Ⓜ B6167F 1989 09 on the die.

DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. The cause is not known. This changes the timing for DMC DMA implicit-stop glitches (the sample must be started 1 APU cycle earlier to trigger the glitches), and it is suspected that it delays DMC IRQ by 1 APU cycle.

CPU=UA6527P 8931S.jpg Runs hot. Revisions without "-" in the date stamp have a ÷16 CPU divider
CPU=UA6527P 9019-BS.jpg Runs hot. Revisions with "-" in the date stamp have a ÷15 CPU divider
CPU=UA6527P 9214-BS 310551.jpg Runs cooler
UA6540 UMC-made clone of 2A07 [5]. Has swapped pulse duty cycles.

Subsequent research implies this is identical to the early 6527P - NTSC tuning tables, ÷16 CPU divider. [6]

CPU=UA6540 8833S.JPG CPU=UA6540-8834S.jpg

UM6557 Believed to be a 100% duplicate of UA6527, for use in SECAM regions.
UM6561xx-1 NES-on-a-chip for NTSC. Revisions "xx" F, AF, BF, CF known. Earlier revisions (which?) CPU half believed identical to UA6527; later revisions correct pulse channel duties.
UM6561xx-2 NES-on-a-chip for PAL-B. Revisions "xx" F, AF, BF, CF known. Earlier revisions (which?) CPU half believed identical to UA6527P; later revisions correct pulse channel duties.

F and AF revision pulse wave duty cycles match RP2A03, and DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.

AF revision observed to have incorrect ASR #imm ($4B) behavior, but other stable illegal instructions work properly.

NOAC=UM6561 AF-2 9440A R81040.jpg

T1818 ??-made NES-on-a-chip, NTSC timing. Believed to exist, but evidence currently scant.
T1818P ??-made NES-on-a-chip[[7]. Requires external 2 KiB RAMs for CPU and PPU. Swapped pulse duty cycles. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.
TA-03N ??-made clone of 2A03G. Pin 30 selects input clock divider?

CPU=TA-03N 6527 9250.jpg

TA-03NP ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15?

CPU=TA-03NP EWP0124.jpg But not this one, this input clock divider is 12.

TA-03NP1 ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? Correct pulse channel duties. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs.

CPU=TA-03NP1 6527P 9231.jpg

PM03 Gradiente-made clone of 2A03G. [8]

CPU=PM03 HI25.jpg

GS870007 (Goldstar??)-made clone of 2A03 - has functioning decimal mode? [9]

CPU=GS87007 8827.jpg

KC-6005 Found in MT777-DX famiclone, behaves exactly like UA6527P

CPU=KC-6005.jpg

6005B CPU=6005B.jpg
2011 CPU=2011.jpg
“2A03E” Both with and without USC insignia

CPU=USC 2A03E 9118S 314531.jpg CPU=2A03E 9122A 422951.jpg

KP2B03E CPU=KP2B03E DHG 44.jpg

If you know of other differences or other revisions, please add them!

See also