Clock rate: Difference between revisions

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The '''clock rate''' of various components in the NES differs between consoles in the USA and Europe due to the different television standards used (NTSC M vs. PAL B). The color encoding method used by the NES (see [[NTSC video]]) requires that the master clock frequency be six times that of the color subcarrier, but this frequency is about 24% higher on PAL than on NTSC. In addition, PAL has more scanlines per field and fewer fields per second than NTSC.
#REDIRECT [[Cycle reference chart]]
Furthermore, the PAL CPU's master clock could have been divided by 15 to preserve the ratio between CPU and PPU speeds, but Nintendo chose to keep the [[wikipedia:Ring counter|Johnson counter]] structure, which always has an even period, and divide by 16 instead.
 
So the main differences between the NTSC and PAL PPUs are depicted in the following table:
{| class="tabular"
! Property
! NTSC (2C02)
! PAL (2C07)
! Dendy
! RGB (2C03)
! RGB (Vs. 4)
! RGB (2C05)
|-
| Master clock speed
| 21.477272 MHz &plusmn; 40 Hz<br/>236.25 MHz ÷ 11 by definition
| 26.601712 MHz &plusmn; 50 Hz<br/>26.6017125 MHz by definition
| Like PAL
| colspan=3 align=center|Like NTSC
|-
| CPU
| Ricoh 2A03
| Ricoh 2A07
| UMC 6527P
| colspan=3 align=center|Ricoh 2A03
|-
| CPU clock speed
| 21.47~ MHz ÷ 12 = 1.789773 MHz<br/>Same as NTSC Amiga clock ÷ 4
| 26.60~ MHz ÷ 16 = 1.662607 MHz
| 26.60~ MHz ÷ 15 = 1.773448 MHz<br/>Same as PAL Amiga clock ÷ 4
| colspan=3 align=center|Like NTSC
|-
| [[APU Frame Counter]] rate
| 60 Hz
| 50 Hz[http://forums.nesdev.org/viewtopic.php?p=160349#p160349]
| 59 Hz[http://forums.nesdev.org/viewtopic.php?p=174970#p174970]
| colspan=3 align=center|Like NTSC
|-
| PPU
| Ricoh 2C02
| Ricoh 2C07
| UMC 6538
| Ricoh 2C03
| Ricoh 2C04-0001 through 2C04-0004
| Ricoh 2C05
|-
| PPU clock speed
| 21.477272 MHz ÷ 4
| 26.601712 MHz ÷ 5
| Like PAL
| colspan=3 align=center|Like NTSC
|-
| PPU dots per CPU cycle
| 3
| 3.2
| 3
| colspan=3 align=center|Like NTSC
|-
| CPU cycles per scanline
| 341 × 4÷12 = 113<sup>2</sup>&frasl;<sub>3</sub>
| 341 × 5÷16 = 106<sup>9</sup>&frasl;<sub>16</sub>
| 341 × 5÷15 = 113<sup>2</sup>&frasl;<sub>3</sub>
| colspan=4 align=center|Like NTSC
|-
| Height of picture
| 240 scanlines
| 239 scanlines
| Like PAL
| colspan="3" align="center"|Like NTSC
|-
| Nominal visible picture height (see [[Overscan]])
| 224 scanlines
| 268 scanlines
| Like PAL
| colspan=3 align=center|Like NTSC
|-
| "Post-render" blanking lines between end of picture and [[NMI]]
| 1 scanline
| 1 scanline
| 51 scanlines
| colspan=3 align=center|Like NTSC
|-
| Length of vertical blanking after NMI
| 20 scanlines (≈ 2273 CPU cycles)
| 70 scanlines (≈ 7459 CPU cycles)
| Like NTSC
| colspan=3 align=center|Like NTSC
|-
| Time during which [[OAM]] can be written
| Vertical or forced blanking
| Only during first 20 scanlines after NMI (≈2131 CPU cycles)
| Like NTSC
| colspan=3 align=center|Like NTSC
|-
| "Pre-render" lines between vertical blanking and next picture
| colspan="6" align="center" | 1 scanline
|-
| Total number of dots per frame
| 341 × 261 + 340.5 = 89341.5<br/>(pre-render line is one dot shorter in every other frame)
| 341 × 312 = 106392
| Like PAL
| colspan=3 align=center| 341 × 262 = 89342
|-
| Total number of CPU cycles per frame
| 89341.5 ÷ 3 = 29780.5
| 106392 ÷ 3.2 = 33247.5
| 106392 ÷ 3 = 35464
| colspan=3 align=center| 89342 ÷ 3 = 29780<sup>2</sup>&frasl;<sub>3</sub>
|-
| Vertical scan rate
| 60.0988 Hz
| 50.0070 Hz
| Like PAL
| colspan=3 align=center|60.0985 Hz
|-
| Color of top border
| colspan="6" align="center" | Always black ($0E)
|-
| [[NTSC video|Side and bottom borders]]
| [[PPU palettes|Palette]] entry at $3F00
| Always black ($0E), [[Overscan#PAL|intruding on left and right 2 pixels and top 1 pixel of picture]]
| Like PAL [https://forums.nesdev.org/viewtopic.php?p=173764#p173764]
| colspan="3" align="center" | Like NTSC[https://forums.nesdev.org/viewtopic.php?p=179705#p179705]
|-
| Color emphasis<br/>(with correlating bit in [[PPUMASK]])
| Blue (D7), green (D6), red (D5)
| Blue (D7), red (D6), green (D5)
| Like PAL
| colspan=3 align=center|Blue, green, red (full scale)
|-
| Other quirks
| Early revisions cannot read back sprite or palette memory
|
|
| Missing $2D and $3D greys
| Permutated palette
| [[PPUCTRL]] and [[PPUMASK]] are swapped; revision ID in [[PPUSTATUS]] (D4-D0)
|}
Some frequencies in the above table are rounded.
 
The 2C03, 2C04, and 2C05 PPUs were all found in Nintendo's [[wikipedia:Nintendo_VS._System|Vs. System]] and [[wikipedia:PlayChoice-10|PlayChoice-10]] (a.k.a. PC10 or PC-10) arcade systems.
Famicom Titler, Famicom TVs, and RGB-modded NES consoles would use either the 2C03 or a 2C05 with glue logic to unswap $2000 and $2001.
(Later RGB mods used a 2C02 in output mode and faked out all palette logic.)
 
The color emphasis bits on the PAL NES have their red and green bits in [[PPUMASK]] swapped
 
The authentic NES sold in Brazil is an NTSC NES with an adapter board to turn the NTSC video into [[wikipedia:PAL-M|PAL-M video]], a variant of PAL using NTSC frequencies but PAL's color modulation.
 
Micro Genius is a clone of the Famicom, manufactured by TXC Corporation of Taiwan and sold under various brand names in the 50 Hz market.<ref>Post by feos on [http://tasvideos.org/forum/viewtopic.php?p=467169#467169 TASVideos] and [https://forums.nesdev.org/viewtopic.php?p=216078#p216078 NESdev]</ref>
Among the best known brands is [[wikipedia:Dendy (console)|Dendy]], distributed in Russia by Steepler, and the attention given by Russian reverse engineers to this clone has led to "Dendy" becoming a common name for all PAL Micro Genius-type famiclones.
Its chipset (UA6527P+UA6538) is designed for compatibility with Famicom games, including games with CPU cycle counting mappers (e.g. [[VRC4]]) and games that use a cycle-timed NMI handler (e.g. ''Balloon Fight'').
This explains the faster CPU divider and longer post-render period vs. the authentic PAL NES.
 
To compensate for these differences, you can [[detect TV system|detect the TV system]] at power-on.
 
== References ==

Latest revision as of 05:39, 20 November 2018