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The '''Famicom Disk System''' was a Japan-exclusive storage device for the Famicom, designed to reduce Nintendo's cost of making copies of games by switching from mask [[ROM]] chips to a storage medium based on Mitsumi's Quick Disk.
[[File:Nintendo-Famicom-Disk-System.jpg|300px|thumb|right|Famicom, FDS RAM adapter, and FDS disk drive]]
Unfortunately for Nintendo, it also reduced the pirates' cost of making copies of games.
<div class="infobox">
<div style="text-align: center">'''FDS'''</div>
{| class="oddf0 floatright"
| '''Company'''
| Nintendo
|-
| '''Complexity'''
| ASIC
|-
| '''Pinout'''
| [[RP2C33 pinout]]
|-
| '''BIOS PRG ROM size'''
| 8K
|-
| '''PRG RAM capacity'''
| 32K
|-
| '''CHR capacity'''
| 8K
|-
| '''Disk capacity'''
| ~64K per side
|-
| '''Mirroring'''
| H or V, switchable
|-
| '''Bus conflicts'''
| No
|-
| '''IRQ'''
| Yes
|-
| '''Audio'''
| Yes
|}</div>
The '''Famicom Disk System''' is a Japan-exclusive storage device for the Famicom, designed to reduce Nintendo's cost of making copies of games by switching from mask [[ROM]] chips to a storage medium based on Mitsumi's Quick Disk.
Unfortunately for Nintendo, it also reduced the pirates' cost of making copies of games. Games are stored on one or multiple disk sides. The [[FDS BIOS]] is used to load data from disks to PRG RAM or VRAM, and games can execute from there.


== .FDS format ==
== Hardware ==
'''fwNES''' was an [[NES emulator]] developed by Fan Wan Yang.  Its most lasting contribution to the NES scene was its disk image file format, an image of the Quick Disk media.


The FDS format (file name suffix <code>.fds</code>) is a way to store Famicom Disk System disk data. It consists of the following sections, in order:
The Famicom disk system comes in two parts: The disk drive and the RAM adapter.
# Header (16 bytes)
# Disk data (65500 * ''x'' bytes)


The format of the header is as follows:
The RAM adapter is a special shaped cartridge that contains the RAM chips and an ASIC with DRAM controller, IRQ hardware, sound generation hardware, serial interface for the disk drive, and parallel port. The Disk Drive has to be powered separately and is only connected to the Famicom/NES via a [[FDS RAM adaptor cable pinout|serial cable]] to the RAM adapter.
* 0-3: Constant $46 $44 $53 $1A ("FDS" followed by MS-DOS end-of-file)
* 4: Number of disk sides in 65500 byte units
* 5-15: Zero filled


Note: Most games are an even number of sides. Ports from NROM were one side. No commercial FDS game had an odd number of sides greater than 1.
Most disk drives contain two motors: a spindle motor that spins the disk at a specific speed, and a stepper motor which moves the read/write head between each circular data track. By comparison, the FDS only contains a single motor that does both at once, so it instead stores the data in a single spiral-shaped track. There is a mechanism that detects when the head reaches the end of the disc and makes it return to the start (making an audible click). Because of this limitation, random access to the disc is impossible, making FDS disk drive data access behave similarly to a reel of tape (but ''much'' faster). Data can only be accessed by spinning the disc, waiting for the head to reach the inner edge of the disc, then waiting again until the desired data file is reached. A complete cycle through the entire disc takes about 7 seconds.


== Overview ==
The disc drive only contains basic electronics, there is no "intelligence" in it; therefore, the serial interface almost directly represents what is stored on the disc.
* PRG ROM : 8 KB BIOS at $E000-$FFFF
* PRG RAM: 32 KB at $6000-$DFFF
* CHR capacity: 8 KB RAM
* Nametable [[mirroring]]: Controlled by mapper
* Subject to [[bus conflict]]s: No
Games are stored on one or multiple disk sides. The FDS BIOS is used to load data from disks to PRG RAM or VRAM, and games can execute form there.


== FDS Disk Side format ==
=== Disks ===


Each disk side must be structured into block as follows :
The FDS disk is a modified version of the Mitsumi Quick Disk.


1, 2, 3, 4, 3, 4, ...., 3, 4
See:
* [[FDS disk format]] - the disk data format and file structure
* [[FDS file format]] (.FDS) - an archival file format for storing and emulating FDS disks


The 3, 4 pattern should be repeated once per file present on the disk.
== Banks ==
 
All Banks are fixed
From the last file, fill the side with all 0 so that the side has exactly 65550 is reached.
* PPU $0000-$1FFF: 8k CHR RAM
 
* CPU $6000-$DFFF: 32k PRG RAM
== Block format ==
* CPU $E000-$FFFF: 8k BIOS PRG ROM
 
=== Disk info block (block 1) ===
 
SIZE  CONTENTS
1      $01
14    FC Disk String  "*NINTENDO-HVC*" (not including the ")
1      Manufacture Code 
        Same code as used in GameBoy(?)
4      Game Name Code
1      Game Version Number (start with $00, increase each revision)
1      Side Number 
          $00: Side-A 
          $01: Side-B
1      Disk Number (fist disk is actually $00)
1      Err.9  (indicate disk # ?, usually $00)
1      Err.10 (indicate disk # ?, usually $00)
1      Boot Read File Code
5      Unknown
3      Manufacture Permit Date
        Recorded in BCD, in the year of "showa"(+1925)
        For example, 21 march 2010 becomes $85, $03, $21 (because 2010-1925 = 85)
10    Unknown
3      Created Date 
        Recorded in BCD, in the year of "showa"(+1925)
9      Unknown
 
The '''*NINTENDO-HVC*''', stored in ASCI standard, strings proves this is a FDS disk, and if the string doesn't exactly match the BIOS will refuse to read the disk further.
If the FDS is started with a disk whose side number and disk number aren't both 0, it will be prompted to insert the first disk side. Some games do however make this number 0 even for the second disk to make it bootable as well.
 
All files which IDs is smaller than the boot read file code will be loaded when the game is booting.
 
The FDS will also refuse to run the game if the first file isn't a nametable type file which is traditionally named "KYODAKU-" and which print a text on the screen.
 
=== File amount block (block 2) ===
 
This block contains the total number of files recorded on disk.  The info in this block is checked only at system boot.  Since there may exist more files than the number recorded in this block, emulators should ignore the value recorded in this block.
 
SIZE  CONTENTS
1        $02
1      File Amount
 
=== File header block  (block 3) ===
 
SIZE    CONTENTS
1        $03
1        File Number 
1        File Indicate Code (file identification code) 
          ID specified at disk-read function call
8        File Name
2        File Address (16-bit little endian)
          the destination address when loading
2        File Size (16-bit little endian)
1        Kind of File 
          0:Program (PRAM) 
          1:Character (CRAM) 
          2:Name table (VRAM)
 
The file Number must go in increasing order, first file is 0.
File IDs can be freely assigned, and this is the number which will decide which file is loaded from the disk (instead of the file number). An ID smaller than the boot number means the file is a boot file, and will be loaded on first startup.
 
File names are uppercase ASCII.
 
=== File data block (block 4) ===
 
SIZE      CONTENTS
1        $04
--        disk data


== Registers ==
== Registers ==


$402x registers are write-only
$402x registers are write-only,
$403x registers are read-only
$403x registers are read-only


 
=== Timer IRQ reload value low ($4020) ===
=== IRQ timer low ($4020) ===


  7  bit  0
  7  bit  0
  ---------
  ---------
  LLLLLLLLL
  LLLL LLLL
  |||| ||||
  |||| ||||
  ++++-++++- 8 LSB of IRQ timer
  ++++-++++- 8 LSB of timer IRQ reload value


=== IRQ timer high ($4021) ===
=== Timer IRQ reload value high ($4021) ===


  7  bit  0
  7  bit  0
  ---------
  ---------
  LLLLLLLLL
  LLLL LLLL
  |||| ||||
  |||| ||||
  ++++-++++- 8 MSB of IRQ timer
  ++++-++++- 8 MSB of timer IRQ reload value
 
Unlike $4022, $4020 and $4021 are not affected by the $4023.0 (disk registers enabled) flag - the reload value can be altered even when disk registers are disabled.


=== IRQ timer enable ($4022) ===
=== Timer IRQ control ($4022) ===


  7  bit  0
  7  bit  0
  ---------
  ---------
  xxxx xxEx
  xxxx xxER
         |
         ||
         +-- Enable IRQ timer
        |-- Timer IRQ Repeat Flag
         +-- Timer IRQ Enabled
 
When $4022 is written to with bit 1 (IRQ enabled) set, the reload value is copied into the IRQ's counter.
Each CPU clock cycle the counter is decremented by one if the enable flag is set.
 
When the counter's value is 0 and the IRQ enable flag is on, the following happens on every CPU cycle:
* An IRQ is generated.
* The IRQ counter is reset to its reload value (contained in $4020+$4021)
* If the IRQ repeat flag is NOT set, the IRQ enabled flag is cleared and the counter stops.


Each CPU clock cycle the timer is decremented by one if the enable flag is set.
Notes:
When the counter reach 0, an IRQ is generated. Read $4030 to acknowledge the IRQ.
* This register is affected by the $4023.0 (Enable disk I/O registers) flag - if disk registers are disabled, it is impossible to start the IRQ counter (writing to $4022 has no effect).
* Clearing $4023.0 will immediately stop the IRQ counter and acknowledge any pending timer IRQs.
* Writing to $4022 with bit 1 (IRQ enabled) cleared will stop the IRQ counter and acknowledge any pending timer IRQs.
* Enabling timer IRQs when the reload value is set to 0 will cause an IRQ immediately. Doing this with the repeat flag enabled will cause an infinite loop of IRQs on every CPU cycle.
* Since the disk transfer routine also uses IRQs, it's very important to disable timer IRQs before doing any access to the disk.


Note : Since the disk transfer routine also uses IRQs, it's very important to disable timer IRQs before doing any access to the disk.
There are only 3 known ways to acknowledge the timer IRQ:
* Read $4030
* Disable timer IRQs by writing to $4022
* Disable disk registers by writing to $4023


=== Master I/O enable ($4023) ===
=== Master I/O enable ($4023) ===
Line 147: Line 124:
         +-- Enable sound I/O registers
         +-- Enable sound I/O registers


This register sounds obscure. FDS bios just writes $00 then $83 to it.
The FDS BIOS writes $00, then $83 to it during reset. The purpose of bit 7 is unknown.
 
Disabling disk registers disables both disk and timer IRQs.


=== Write data register ($4024) ===
=== Write data register ($4024) ===


The data that this register is programmed with will be the next 8-bit quantity to load into the shift register (next time the byte transfer flag raises), and to be shifted out and appear on pin 5 of the RAM adaptor cable (2C33 pin 52).
The data that this register is programmed with will be the next 8-bit quantity to load into the shift register (next time the byte transfer flag raises), and to be shifted out and appear on pin 5 of the RAM adapter cable (2C33 pin 52).
 
Writing to this register acknowledges disk IRQs.{{Citation needed}}


=== FDS Control ($4025) ===
=== FDS Control ($4025) ===
  7  bit  0
  7  bit  0
  ---------
  ---------
  IS1B MRTD
  IE1C MRDT
  |||| ||||
  |||| ||||
  |||| |||+- Drive Motor Control 
  |||| |||+- Transfer Reset
  |||| |||    0: Stop motor
  |||| |||    0: Reset transfer timing to the initial state.
|||| |||    1: Turn on motor
  |||| ||+-- Drive Motor Control (0: start, 1: stop)
|||| ||+-- Transfer Reset
  |||| |+--- Transfer Mode (0: write; 1: read)
|||| ||        Set 1 to reset transfer timing to the initial state.
  |||| +---- Mirroring (0: vertical; 1: horizontal)
  |||| |+--- Read / Write mode
  |||+------ CRC Transfer Control (1: transfer CRC value)
  |||| |     (0: write; 1: read)
  ||+------- Unknown, always set to '1'
  |||| +---- Mirroring (0: horizontal; 1: vertical)
  |+-------- CRC Enabled (0: disable/reset, 1: enable)
  |||+------ CRC control (set during CRC calculation of transfer)
  +--------- Interrupt Enabled
  ||+------- Always set to '1'
               1: Generate an IRQ every time the byte transfer flag is raised.
  |+-------- Read/Write Start 
|            Turn on motor.  Set to 1 when the drive becomes ready for read/write
  +--------- Interrupt Transfer 
              0: Transfer without using IRQ
               1: Enable IRQ when the drive becomes ready for


A FDS game that wants to change mirroring probably don't want to touch motor related bits, so it should do a read-modify-write from the pseudo registers (see below).
Notes:
* Disabling the CRC resets its state. The FDS BIOS disables the CRC between file blocks, then enables it before accessing each file block to calculate/verify their CRC values.
* To change the mirroring on the fly, a read-modify-write of its [[FDS BIOS#Zero-page variables|mirror]] should be done to prevent altering unrelated bits.
 
Writing to this register acknowledges disk IRQ.


=== External connector ($4026) ===
=== External connector ($4026) ===
Line 180: Line 160:
Output of expansion terminal where there's a shutter on the back of the ram card. The outputs of $4026 (open-collector with 4.7K ohm pull-ups (except on bit 7)), are shared with the inputs on $4033.
Output of expansion terminal where there's a shutter on the back of the ram card. The outputs of $4026 (open-collector with 4.7K ohm pull-ups (except on bit 7)), are shared with the inputs on $4033.


=== Disk Status Register 0 ($4030) ===
=== Disk Status register ($4030) ===
  7  bit  0
  7  bit  0
  ---------
  ---------
  IExB xxTD
  IExB xxTD
  ||||  ||
  || |  ||
  ||||  |+- Timer Interrupt (1: an IRQ occurred)
  || |  |+- Timer Interrupt (1: an IRQ occurred)
  ||||  +-- Byte transfer flag. Set every time 8 bits have been transfered between the RAM adaptor & disk drive (service $4024/$4031).  
  || |  +-- Byte transfer flag. Set every time 8 bits have been transferred between the RAM adaptor & disk drive (service $4024/$4031).  
  ||||      Reset when $4024, $4031, or $4030 has been serviced.
  || |      Reset when $4024, $4031, or $4030 has been serviced.
  |||+------ CRC control (0: CRC passed; 1: CRC error)
  || +------ CRC control (0: CRC passed; 1: CRC error)
  |+-------- End of Head (1 when disk head is on the most inner track)
  |+-------- End of Head (1 when disk head is on the most inner track)
  +--------- Disk Data Read/Write Enable (1 when disk is readable/writable)
  +--------- Disk Data Read/Write Enable (1 when disk is readable/writeable)
 
Reading this register acknowledges timer and disk IRQs.
 
=== Read data register ($4031) ===
=== Read data register ($4031) ===


This register is loaded with the contents of an internal shift register every time the byte transfer flag raises. The shift register recieves it's serial data via pin 9 of the RAM adaptor cable (2C33 pin 51).
This register is loaded with the contents of an internal shift register every time the byte transfer flag raises. The shift register receives its serial data via pin 9 of the RAM adapter cable (2C33 pin 51).
 
Reading this register acknowledges disk IRQs.


=== Disk drive status register ($4032) ===
=== Disk drive status register ($4032) ===
Line 202: Line 186:
       |||
       |||
       ||+- Disk flag  (0: Disk inserted; 1: Disk not inserted)
       ||+- Disk flag  (0: Disk inserted; 1: Disk not inserted)
       |+-- Ready flag (0: Disk read; 1: Disk not ready)
       |+-- Ready flag (0: Disk readу; 1: Disk not ready)
       +--- Protect flag (0: Not write protected; 1: Write protected or disk ejected)
       +--- Protect flag (0: Not write protected; 1: Write protected or disk ejected)
Reading this register acknowledges disk IRQs.{{Citation needed}}


=== External connector read ($4033) ===
=== External connector read ($4033) ===
Line 211: Line 197:
  |||| ||||
  |||| ||||
  |+++-++++- Input from expansion terminal where there's a shutter on the back of the ram card.
  |+++-++++- Input from expansion terminal where there's a shutter on the back of the ram card.
  +--------- Battery status (0: Good; 1: Voltage is low).
  +--------- Battery status (0: Voltage is low; 1: Good).


When a bit is clear in $4026 port it will read back as '0' here (including battery bit) because of how open collector input works.
When a bit is clear in $4026 port it will read back as '0' here (including battery bit) because of how open collector input works. Battery bit should be checked when the motor is on, otherwise it always will be read as 0.


=== Sound ($4040-$4089) ===
=== Sound ($4040-$4092) ===


For details on sound information, see [[FDS_audio|FDS audio]].
For details on sound information, see [[FDS_audio|FDS audio]].


== Pseudo-registers ==
== BIOS ==
Those registers are used by the FDS bios and FDS programs. They are used to overcome the problem that NES/FDS registers are write only, so it is effectively possible to modify only one bit of them without affecting other bits.


[$FF]:  value last written to [[$2000]]  $80 on reset.
The FDS contains a fixed 8KB BIOS at $E000-FFFF. This controls the Famicom at power-on and reset, dispatches the NMI and IRQ, and offers an API for accessing the [[FDS disk format|data on disk]].
[$FE]:  value last written to [[$2001]]  $06 on reset
[$FD]:  value last written to [[$2005]]#1 0'd on reset.
[$FC]:  value last written to [[$2005]]#2 0'd on reset.
[$FB]:  value last written to [[$4016]]  0'd on reset.
[$FA]:  value last written to $4025  $2E on reset.
[$F9]:  value last written to $4026  $FF on reset.
$F5..$F8 : Used by controller read routines
$00..$0F is used as temporary memory for the BIOS. The main program can use it as temporary memory too.


Those values are used by the BIOS to determine action on interrupt.
See: [[FDS BIOS]]
($0102): PC action on reset
[$0101]: PC action on IRQ. set to $80 on reset
[$0100]: PC action on NMI. set to $C0 on reset
($DFFE): disk game IRQ vector    (if [$0101] = 11xxxxxxB)
($DFFC): disk game reset vector  (if ($0102) = $5335, or $AC35)
($DFFA): disk game NMI vector #3 (if [$0100] = 11xxxxxxB)
($DFF8): disk game NMI vector #2 (if [$0100] = 10xxxxxxB)
($DFF6): disk game NMI vector #1 (if [$0100] = 01xxxxxxB)


A few important notes :
== See Also ==
- $102 indicate reset type : $AC = first boot of the game, $53 = the game was soft-reseted by the user
- To use your own IRQ routine, you must manually write $c0 to $101
- There is 3 possible NMI vectors, #3 is used by default. If you only use one, then make all 3 identical.


== BIOS calls ==
* [[FDS BIOS]]
* [[FDS disk format]]
* [[FDS file format]] ('''.FDS''')
* [[FDS audio]]
* [[FDS RAM adaptor cable pinout]]
* [[RP2C33 pinout]]
* [[iNES mapper 020|iNES mapper 20]] - Reserved for FDS dumps, but not widely used for it.
* [[TNES]] - Nintendo 3DS Virtual Console ROM format with support for FDS disk images.
* [https://github.com/bbbradsmith/NES-ca65-example/tree/fds Github repository:] Simple FDS example for ca65
* [//forums.nesdev.org/viewtopic.php?p=194826#p194826 Forum post:] Skipping the FDS license screen


To be written
== References ==


== References ==
* [//nesdev.org/FDS%20technical%20reference.txt FDS technical reference.txt] by Brad Taylor (old/outdated)
* [http://nesdev.parodius.com/FDSListWIN.zip FDS Lister by ccovell]
* [http://cmpslv2.starfree.jp/Famic/Famdis.htm Enri's Famicom Disk System page] (Japanese)
* [https://web.archive.org/web/20091023182159/http://www2.odn.ne.jp/~haf09260/Famic/Famdis.htm Enri's Famicom Disk System page] (Japanese) (old/outdated)
* [//nesdev.org/fds-nori.txt fds-nori.txt] - FDS reference in Japanese by Nori (old/outdated)
* [https://www.chrismcovell.com/software.html FDS List] by ccovell - command line utility to inspect FDS disk image contents.
* [https://www.chrismcovell.com/fds-lister.html FDS Lister] by ccovell - utility to inspect FDS disk contents that runs on an FDS.
* [//forums.nesdev.org/viewtopic.php?p=194867#p194867 Forum post]: .fds format: Can checksums be heuristically detected? - Includes a CRC implementation in C.
* [//forums.nesdev.org/viewtopic.php?f=3&t=16507 Forum post]: FDS IRQ reload flag/value
<references/>
 
[[Category:Mappers using $4020-$5FFF]][[Category:Mappers with cycle IRQs]]

Latest revision as of 07:51, 20 April 2024

Famicom, FDS RAM adapter, and FDS disk drive
FDS
Company Nintendo
Complexity ASIC
Pinout RP2C33 pinout
BIOS PRG ROM size 8K
PRG RAM capacity 32K
CHR capacity 8K
Disk capacity ~64K per side
Mirroring H or V, switchable
Bus conflicts No
IRQ Yes
Audio Yes

The Famicom Disk System is a Japan-exclusive storage device for the Famicom, designed to reduce Nintendo's cost of making copies of games by switching from mask ROM chips to a storage medium based on Mitsumi's Quick Disk. Unfortunately for Nintendo, it also reduced the pirates' cost of making copies of games. Games are stored on one or multiple disk sides. The FDS BIOS is used to load data from disks to PRG RAM or VRAM, and games can execute from there.

Hardware

The Famicom disk system comes in two parts: The disk drive and the RAM adapter.

The RAM adapter is a special shaped cartridge that contains the RAM chips and an ASIC with DRAM controller, IRQ hardware, sound generation hardware, serial interface for the disk drive, and parallel port. The Disk Drive has to be powered separately and is only connected to the Famicom/NES via a serial cable to the RAM adapter.

Most disk drives contain two motors: a spindle motor that spins the disk at a specific speed, and a stepper motor which moves the read/write head between each circular data track. By comparison, the FDS only contains a single motor that does both at once, so it instead stores the data in a single spiral-shaped track. There is a mechanism that detects when the head reaches the end of the disc and makes it return to the start (making an audible click). Because of this limitation, random access to the disc is impossible, making FDS disk drive data access behave similarly to a reel of tape (but much faster). Data can only be accessed by spinning the disc, waiting for the head to reach the inner edge of the disc, then waiting again until the desired data file is reached. A complete cycle through the entire disc takes about 7 seconds.

The disc drive only contains basic electronics, there is no "intelligence" in it; therefore, the serial interface almost directly represents what is stored on the disc.

Disks

The FDS disk is a modified version of the Mitsumi Quick Disk.

See:

Banks

All Banks are fixed

  • PPU $0000-$1FFF: 8k CHR RAM
  • CPU $6000-$DFFF: 32k PRG RAM
  • CPU $E000-$FFFF: 8k BIOS PRG ROM

Registers

$402x registers are write-only, $403x registers are read-only

Timer IRQ reload value low ($4020)

7  bit  0
---------
LLLL LLLL
|||| ||||
++++-++++- 8 LSB of timer IRQ reload value

Timer IRQ reload value high ($4021)

7  bit  0
---------
LLLL LLLL
|||| ||||
++++-++++- 8 MSB of timer IRQ reload value

Unlike $4022, $4020 and $4021 are not affected by the $4023.0 (disk registers enabled) flag - the reload value can be altered even when disk registers are disabled.

Timer IRQ control ($4022)

7  bit  0
---------
xxxx xxER
       ||
       |-- Timer IRQ Repeat Flag
       +-- Timer IRQ Enabled

When $4022 is written to with bit 1 (IRQ enabled) set, the reload value is copied into the IRQ's counter. Each CPU clock cycle the counter is decremented by one if the enable flag is set.

When the counter's value is 0 and the IRQ enable flag is on, the following happens on every CPU cycle:

  • An IRQ is generated.
  • The IRQ counter is reset to its reload value (contained in $4020+$4021)
  • If the IRQ repeat flag is NOT set, the IRQ enabled flag is cleared and the counter stops.

Notes:

  • This register is affected by the $4023.0 (Enable disk I/O registers) flag - if disk registers are disabled, it is impossible to start the IRQ counter (writing to $4022 has no effect).
  • Clearing $4023.0 will immediately stop the IRQ counter and acknowledge any pending timer IRQs.
  • Writing to $4022 with bit 1 (IRQ enabled) cleared will stop the IRQ counter and acknowledge any pending timer IRQs.
  • Enabling timer IRQs when the reload value is set to 0 will cause an IRQ immediately. Doing this with the repeat flag enabled will cause an infinite loop of IRQs on every CPU cycle.
  • Since the disk transfer routine also uses IRQs, it's very important to disable timer IRQs before doing any access to the disk.

There are only 3 known ways to acknowledge the timer IRQ:

  • Read $4030
  • Disable timer IRQs by writing to $4022
  • Disable disk registers by writing to $4023

Master I/O enable ($4023)

7  bit  0
---------
xxxx xxSD
       ||
       |+- Enable disk I/O registers
       +-- Enable sound I/O registers

The FDS BIOS writes $00, then $83 to it during reset. The purpose of bit 7 is unknown.

Disabling disk registers disables both disk and timer IRQs.

Write data register ($4024)

The data that this register is programmed with will be the next 8-bit quantity to load into the shift register (next time the byte transfer flag raises), and to be shifted out and appear on pin 5 of the RAM adapter cable (2C33 pin 52).

Writing to this register acknowledges disk IRQs.[citation needed]

FDS Control ($4025)

7  bit  0
---------
IE1C MRDT
|||| ||||
|||| |||+- Transfer Reset
|||| |||     0: Reset transfer timing to the initial state.
|||| ||+-- Drive Motor Control (0: start, 1: stop)
|||| |+--- Transfer Mode (0: write; 1: read)
|||| +---- Mirroring (0: vertical; 1: horizontal)
|||+------ CRC Transfer Control (1: transfer CRC value)
||+------- Unknown, always set to '1'
|+-------- CRC Enabled (0: disable/reset, 1: enable)
+--------- Interrupt Enabled
             1: Generate an IRQ every time the byte transfer flag is raised.

Notes:

  • Disabling the CRC resets its state. The FDS BIOS disables the CRC between file blocks, then enables it before accessing each file block to calculate/verify their CRC values.
  • To change the mirroring on the fly, a read-modify-write of its mirror should be done to prevent altering unrelated bits.

Writing to this register acknowledges disk IRQ.

External connector ($4026)

Output of expansion terminal where there's a shutter on the back of the ram card. The outputs of $4026 (open-collector with 4.7K ohm pull-ups (except on bit 7)), are shared with the inputs on $4033.

Disk Status register ($4030)

7  bit  0
---------
IExB xxTD
|| |   ||
|| |   |+- Timer Interrupt (1: an IRQ occurred)
|| |   +-- Byte transfer flag. Set every time 8 bits have been transferred between the RAM adaptor & disk drive (service $4024/$4031). 
|| |       Reset when $4024, $4031, or $4030 has been serviced.
|| +------ CRC control (0: CRC passed; 1: CRC error)
|+-------- End of Head (1 when disk head is on the most inner track)
+--------- Disk Data Read/Write Enable (1 when disk is readable/writeable)

Reading this register acknowledges timer and disk IRQs.

Read data register ($4031)

This register is loaded with the contents of an internal shift register every time the byte transfer flag raises. The shift register receives its serial data via pin 9 of the RAM adapter cable (2C33 pin 51).

Reading this register acknowledges disk IRQs.

Disk drive status register ($4032)

7  bit  0
---------
xxxx xPRS
      |||
      ||+- Disk flag  (0: Disk inserted; 1: Disk not inserted)
      |+-- Ready flag (0: Disk readу; 1: Disk not ready)
      +--- Protect flag (0: Not write protected; 1: Write protected or disk ejected)

Reading this register acknowledges disk IRQs.[citation needed]

External connector read ($4033)

7  bit  0
---------
BIII IIII
|||| ||||
|+++-++++- Input from expansion terminal where there's a shutter on the back of the ram card.
+--------- Battery status (0: Voltage is low; 1: Good).

When a bit is clear in $4026 port it will read back as '0' here (including battery bit) because of how open collector input works. Battery bit should be checked when the motor is on, otherwise it always will be read as 0.

Sound ($4040-$4092)

For details on sound information, see FDS audio.

BIOS

The FDS contains a fixed 8KB BIOS at $E000-FFFF. This controls the Famicom at power-on and reset, dispatches the NMI and IRQ, and offers an API for accessing the data on disk.

See: FDS BIOS

See Also

References

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