File:Apu address.jpg: Revision history

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11 May 2011

  • curprev 03:1803:18, 11 May 2011‎ Quietust talk contribs‎ 681 bytes −10‎ it also overrides the noise channel's LFSR output and appears to also stop the triangle channel from being clocked; I don't know what it does to DPCM, but it's probably something similar
  • curprev 03:0303:03, 11 May 2011‎ Quietust talk contribs‎ 691 bytes +12‎ setting $401A.7 prevents the square channels from outputting 0000, whether from the duty cycle generator, the sweep unit, or the length counter; the effect on triangle/noise/PCM is still unclear

27 February 2011

24 January 2011

  • curprev 15:3115:31, 24 January 2011‎ Quietust talk contribs‎ m 631 bytes +122‎ anybody capable of interpreting these images is welcome to figure out how to enable these extra registers...
  • curprev 15:2615:26, 24 January 2011‎ Quietust talk contribs‎ 509 bytes +509‎ The NES APU's address decoder, generating enables for all reads/writes within $4000-$401F. Of very special note are the 4 signals at the very top for readable registers at $4018 (pulse 0 output on D0-D3 and pulse 1 output on D4-D7), $4019 (triangle outpu
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