File:Apu address.jpg

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Revision as of 03:03, 11 May 2011 by Quietust (talk | contribs) (setting $401A.7 prevents the square channels from outputting 0000, whether from the duty cycle generator, the sweep unit, or the length counter; the effect on triangle/noise/PCM is still unclear)
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The NES APU's address decoder, generating enables for all reads/writes within $4000-$401F.

Of very special note are the 4 signals at the very top for readable registers at $4018 (pulse 0 output on D0-D3 and pulse 1 output on D4-D7), $4019 (triangle output on D0-D3, noise output on D4-D7), $401A (DPCM output on D0-D6), and a writable register at $401A (set triangle position to D0-D4, and seemingly lock channel outputs using D7); all 4 of these signals have an additional enable which seems to come from the vicinity of pin 30.

Source: http://uxul.org/~noname/chips/cpu-5/stitched/final/ http://uxul.org/~noname/chips/cpu-2/no-metal/stitched/final/

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current21:56, 21 September 2021Thumbnail for version as of 21:56, 21 September 20211,314 × 400 (294 KB)>Maintenance script== Summary == Importing file

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