iNES Mapper 006 is used for ROM images that have been extracted from disk images for the Bung (Super) Game Doctor or Front Fareast Magicard RAM cartridges and that use Game Doctor Mode 1 or 8 KiB Banking Mode (exclusively or non-exclusively). Extracted games that exclusively use the other banking modes can be run using their normal iNES mapper equivalents. iNES Mapper 008 specifies Game Doctor Mode 4, which makes it a duplicate of INES Mapper 066.

Banks

CPU $6000-$7FFF: 8 KiB of PRG-RAM. If the iNES header specifies a 512-byte "trainer", it must be loaded to $7000-$71FF, be writable, and (on a hard reset) initialized by JSRing to $7003 before JMPing to the game's reset vector.
CPU $8000-$FFFF: 32 KiB of PRG-"ROM", banked in various amounts from 256 KiB total depending on the banking mode.
PPU $0000-$1FFF: 8 KiB of CHR-RAM, banked in 8 KiB amounts from 32 KiB total.

Game Doctor Banking Modes

Write-only register at $42FC-$42FF:
A~FEDC BA98 7654 3210  D~7654 3210
  -------------------    ---------
  0100 0010 1111 11bM    BBBM ....
                   |+----|||+------ Set nametable mirroring type
                   |     |||         0: One-screen, page 0
                   |     |||         1: One-screen, page 1
                   |     |||         2: Vertical
                   |     |||         3: Horizontal
                   +-----|||------- 0: PRG-ROM is writeable, latch is disabled
                         |||        1: PRG-ROM is write-protected, latch is enabled
                         +++------- Select Game Doctor Banking mode

Because the RAM cartridge has no other means of masking PRG-/CHR-ROM addresses, UNROM vs. UOROM and CNROM-128 vs. CNROM-256 are explicitly differentiated.
When changing from a mode that allows changing CHR-RAM banks to one that does not, the previously-chosen CHR-RAM bank remains active.
The latch at $8000-$FFFF is only active when PRG-"ROM" is write-protected. A few games temporarily write-enable PRG-"ROM" to change the reset handler after initialization.

Mode 0: UNROM

16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D2 of data latch at CPU $8000-$FFFF
16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
8 KiB of write-enabled CHR-RAM

Mode 1: Custom

A hybrid of UNROM (fixed bank 7), UOROM (256 KiB total PRG-ROM size), and UN1ROM (left shift by 2) with 32 KiB of CHR-RAM.

16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D2..D6 of data latch at CPU $8000-$FFFE (not $FFFF!)
16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
8 KiB write-enabled CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFE (not $FFFF!)

Mode 2: UOROM

16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D3 of data latch at CPU $8000-$FFFF
16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #15
8 KiB of write-enabled CHR-RAM

Mode 3: Reverse UOROM

16 KiB PRG-ROM bank at CPU $8000-$BFFF, fixed to bank #15
16 KiB PRG-ROM bank at CPU $C000-$FFFF, switched by D0..D3 of data latch at CPU $8000-$FFFF
8 KiB of write-enabled CHR-RAM

Mode 4: GNROM

32 KiB PRG-ROM bank at CPU $8000-$FFFF, switched by D4..D5 of data latch at CPU $8000-$FFFF
8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF

Mode 5: CNROM-256

32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #7
8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF

Mode 6: CNROM-128

32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
8 KiB of write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0 of data latch at CPU $8000-$FFFF

Mode 7: NROM-256

32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF

8 KiB Banking Mode

Write-only register at $43FE-$43FF:
A~FEDC BA98 7654 3210
  -------------------
  0100 0011 1111 111M
                    |
                    +- Enable/Disable 4M PRG Banking Mode
                        0: Enable
                        1: Disable

Banks:
- 8 KiB PRG-ROM bank at CPU $8000-$9FFF, switched by D2..D7 of data latch at CPU $8000-$9FFF
- 8 KiB PRG-ROM bank at CPU $A000-$BFFF, switched by D2..D7 of data latch at CPU $A000-$BFFF
- 8 KiB PRG-ROM bank at CPU $C000-$DFFF, switched by D2..D7 of data latch at CPU $C000-$DFFF
- 8 KiB PRG-ROM bank at CPU $E000-$FFFF, switched by D2..D7 of data latch at CPU $E000-$FFFF
- 8 KiB CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
If enabled, it has precedence over the Game Doctor banking modes in everything but CHR-RAM write-protection.
The four data latches accept values written even when 8 KiB Banking Mode is not active, and will take effect once $43FE is written to afterwards.

FDS Write Data ($4024)

This register is not part of the RAM cartridge, but part of the FDS RAM adapter that originally attached to it. A few games abusing the FDS Disk Data IRQ for frame timing write any value to this register to acknowledge a pending IRQ.

FDS Control ($4025)

This register is not part of the RAM cartridge, but part of the FDS RAM adapter that originally attached to it. A few games abuse the FDS Disk Data IRQ for frame timing. If bit 7 is set, the FDS RAM adapter will generate IRQs every 1,792 cycles of the 21.4772 MHz master clock, or after every 149+1/3 CPU cycles.

Cycle IRQ Counter Low Byte ($4100)

This is the low byte of a 16-bit counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000. Writing to this register also acknowledges the IRQ.

Cycle IRQ Counter High Byte ($4101)

This is the high byte of a 16-bit counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000.

Notes

Mapper 6 Info on the FFE mapper. By FanWen Yang (outdated).
Info on various Famicom "copiers"

INES Mapper 006

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