INES Mapper 014: Difference between revisions

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(try omitting redundant definition of VRC2 here)
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GoodNES 3.1.4 has Samurai Spirits as a UNIF dump with MAPR ''UNL-SL1632'' and as [[iNES Mapper 116]]. However, the documentation for mapper 116 implies that SL1632 is substantively different.
GoodNES 3.1.4 has Samurai Spirits as a UNIF dump with MAPR ''UNL-SL1632'' and as [[iNES Mapper 116]]. However, the documentation for mapper 116 implies that SL1632 is substantively different.


== MMC3 Mode Control: $A131 ==
== Mapper Mode Control: $A131 ==


  7  bit  0
  7  bit  0
Line 13: Line 13:
  A.B. C.M.
  A.B. C.M.
         |
         |
         +- MMC3 mode (1: on, 0: off)
         +- Mode (1: MMC3, 0: VRC2)


* When M is set, writes to $8000-FFFF operate mostly as normal for [[MMC3]].
* When M is set, writes to $8000-FFFF operate mostly as normal for [[MMC3]].
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* If C is set add $100 to upper two 1k CHR banks.
* If C is set add $100 to upper two 1k CHR banks.


== MMC3 Mode Set ==
== MMC3 Mode ==


Note that when the MMC3 Mode bit is set, this mapper operates mostly like the MMC3, except the $A000-BFFE even register does not control the nametable mirroing (it can only be controlled with the MMC3 mode clear). Additionally, a write to the specific address $A131 will alter the MMC3 Mode bit as above.
Note that when the Mode bit is set to MMC3, this mapper operates mostly like the MMC3, except the $A000-BFFE even register does not control the nametable mirroring (it can only be controlled when in VRC2 mode). Additionally, a write to the specific address $A131 will alter the MMC3 Mode bit as above.


* $8000-9FFE even - as MMC3
* $8000-9FFE even - as MMC3
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There may be a conflict between $A131 and the $A001-BFFF odd register if PRG RAM is present. The Nestopia implementation also writes to the corresponding MMC3 register when writing $A131 if the MMC3 Mode bit is set.
There may be a conflict between $A131 and the $A001-BFFF odd register if PRG RAM is present. The Nestopia implementation also writes to the corresponding MMC3 register when writing $A131 if the MMC3 Mode bit is set.


== MMC3 Mode Clear ==
== VRC2 Mode ==


This mode is very similar to [[VRC2]].
This mode is very similar to [[VRC2]]b.


When the MMC3 Mode bit is clear, PRG banking is controlled by a 2 alternative registers, and CHR banking is controlled by 8 alternative registers. These banking registers are independent of the banking registers used when MMC3 Mode is set.
These banking registers are independent of the banking registers used when MMC3 Mode is set.


* PRG bank 0 - 8k at $8000-9FFF
* $8000-$8FFC - as VRC2
* PRG bank 1 - 8k at $A000-BFFF
** $8001, $8002, $8003, and their mirrors do not respond
* PRG fixed - 16k at $C000-FFFF (fixed to last bank)
* $9000-$9FFC - subset of VRC2
 
** $9001, $9002, $9003, and their mirrors do not respond
* CHR bank 0 - 1k at $0000-03FF
** It is unclear whether the 2s bit exists, supporting H/V/1a/1b mirroring, or just the 1s bit (as the MMC3)
* CHR bank 1 - 1k at $0400-07FF
* $A000-$AFFC - as VRC2
* CHR bank 2 - 1k at $0800-0BFF
** $A001, $A002, $A003, and their mirrors do not respond
* CHR bank 3 - 1k at $0C00-0FFF
* $B000-$EFFF - superset of VRC2b
* CHR bank 4 - 1k at $1000-13FF
** Reportedly the $800s bit should be ORed into the 2s bit to select which CHR register is updated. This is odd: perhaps this actually describes two different versions of the hardware. (If so, what other games use it?)
* CHR bank 5 - 1k at $1400-17FF
* CHR bank 6 - 1k at $1800-1BFF
* CHR bank 7 - 1k at $1C00-1FFF
 
=== $8000-8FFC (0 of 4) ===
* Selects 8k PRG bank at $8000-9FFF
* Only responds if address &3 is 0
* The actual VRC2 ignores A0 and A1, instead of requiring they both be 0.
 
=== $9000-9FFC (0 of 4) ===
 
7  bit  0
---------
.... ...M
        |
        +- [[Mirroring]] (0: vertical; 1: horizontal)
 
* Selects nametable mirroring. Note that this is the ONLY interface to control mirroring: it cannot be set when in MMC3 mode.
* Only responds if address &3 is 0
* It is unclear whether this is actually a two-bit value as in the VRC2, supporting 1-screen mirroring.
 
=== $A000-AFFC (0 of 4) ===
* Selects 8k PRG bank at $A000-EFFF
* Only responds if address &3 is 0
 
=== $B000-E003 ===
The address bits select one of 8 CHR bank registers in an unusual way:
 
15      bit      0
-------------------
.ABC D... .... ..EF
CHR bank register = ((%ABC - 3) << 1) | %D | %E
 
The write to $B000-E003 sets only 4 bits of the CHR bank, selected by the least significant bit of the address (F).
 
if (!F)
    register = (register & $F0) | (data & $0F)
else
    register = (register & $0F) | ((data << 4) & $F0)
 
When D is clear, this is identical to [[VRC2]]b. The bitwise OR is odd: perhaps this actually describes two different versions of the hardware (if so, what other games use it?)

Revision as of 02:19, 22 October 2014


iNES Mapper 014 is an MMC3 variant mapper used in the pirate port of Samurai Spirits by Rex Game Soft. It is very similar to an MMC3, but contains an alternative mode that when used controls banking and mirroring independently of the normal MMC3 mode.

This mapper is not widely supported by emulators. The following notes are based on Nestopia's SOMERITEAM SL-1632 mapper implementation.

GoodNES 3.1.4 has Samurai Spirits as a UNIF dump with MAPR UNL-SL1632 and as iNES Mapper 116. However, the documentation for mapper 116 implies that SL1632 is substantively different.

Mapper Mode Control: $A131

7  bit  0
---------
A.B. C.M.
       |
       +- Mode (1: MMC3, 0: VRC2)
  • When M is set, writes to $8000-FFFF operate mostly as normal for MMC3.
  • When M is clear, alternative functions appear (see MMC3 Mode Clear below).
  • When M is written, the CHR and PRG banks must be switched either to their MMC3 banks (MMC3 Mode Set), or the alternative banks (MMC3 Mode Clear).

In MMC3 mode, bits 7, 5, and 3 of this register also control high bits of the CHR banks, allowing 512k of CHR ROM. This works in conjunction with the current 2k/1k CHR banking mode.

  • If A is set add $100 to both 2k CHR banks.
  • If B is set add $100 to lower two 1k CHR banks.
  • If C is set add $100 to upper two 1k CHR banks.

MMC3 Mode

Note that when the Mode bit is set to MMC3, this mapper operates mostly like the MMC3, except the $A000-BFFE even register does not control the nametable mirroring (it can only be controlled when in VRC2 mode). Additionally, a write to the specific address $A131 will alter the MMC3 Mode bit as above.

  • $8000-9FFE even - as MMC3
  • $8001-9FFF odd - as MMC3
  • $A000-BFFE even - ignored
  • $A001-BFFF odd - as MMC3
  • $C000-DFFE even - as MMC3
  • $C001-DFFF odd - as MMC3
  • $E000-FFFE even - as MMC3
  • $E001-FFFF odd - as MMC3

There may be a conflict between $A131 and the $A001-BFFF odd register if PRG RAM is present. The Nestopia implementation also writes to the corresponding MMC3 register when writing $A131 if the MMC3 Mode bit is set.

VRC2 Mode

This mode is very similar to VRC2b.

These banking registers are independent of the banking registers used when MMC3 Mode is set.

  • $8000-$8FFC - as VRC2
    • $8001, $8002, $8003, and their mirrors do not respond
  • $9000-$9FFC - subset of VRC2
    • $9001, $9002, $9003, and their mirrors do not respond
    • It is unclear whether the 2s bit exists, supporting H/V/1a/1b mirroring, or just the 1s bit (as the MMC3)
  • $A000-$AFFC - as VRC2
    • $A001, $A002, $A003, and their mirrors do not respond
  • $B000-$EFFF - superset of VRC2b
    • Reportedly the $800s bit should be ORed into the 2s bit to select which CHR register is updated. This is odd: perhaps this actually describes two different versions of the hardware. (If so, what other games use it?)
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