|
|
| (15 intermediate revisions by 2 users not shown) |
| Line 1: |
Line 1: |
| [[Category:INES Mappers|017]][[Category:Mappers with cycle IRQs]][[Category:Mappers with scanline IRQs]] | | {{DEFAULTSORT:017}}[[Category:INES Mappers]][[Category:Mappers with cycle IRQs]][[Category:Mappers with scanline IRQs]][[Category:Mappers with ROM nametables]] |
| iNES Mapper 017 is used for ROM images that have been converted from disk images for the ''Front FarEast Super Magic Card'' copiers. All of these ROM images have been modified to use the copier's idiosyncratic bankswitch registers. | | '''iNES Mapper 017''' denotes ROM images that have been extracted from disk images for the ''Front Fareast Super Magic Card'' [[RAM cartridge]]. They represent games whose [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Super_Magic_Card_disks|Doctor Header file]] denotes a Super Magic Card disk (byte $0 bit 7 set, byte $7=$AA). Refer to the [[Super Magic Card]] article for details on bankswitching. The Super Magic Card's registers are initialized to: |
| | ; Play mode, WRAM bank 0, 1 KiB CHR mode enabled |
| | [[Super_Magic_Card#Super_Magic_Card_mode_.28.244500.2C_write-only.29|$4500]] = $47 |
| | |
| | ; PRG memory write-protected, two-screen mirroring |
| | [[Super_Magic_Card#1M_banking_mode_.28.2442FC-.2442FF.2C_write-only.29|$42FF]] = $20 | (verticalMirroring? 0x00: 0x10) |
| | |
| | ; 4M banking mode enabled |
| | [[Super_Magic_Card#2M.2F4M_PRG_banking_mode_.28.2443FC-.2443FF.2C_write-only.29|$43FC]] = $00 |
| | |
| | ; Initial PRG register content |
| | $4504 = Number of 8 KiB PRG banks -4 |
| | $4505 = Number of 8 KiB PRG banks -3 |
| | $4506 = Number of 8 KiB PRG banks -2 |
| | $4507 = Number of 8 KiB PRG banks -1 (originally [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Super_Magic_Card_disks|Doctor Header file]] byte $5) |
|
| |
|
| Unlike the ''[[INES Mapper 006|Bung Game Doctor]]'', the Super Magic Card has 256 KiB of CHR-RAM, allowing an entire game's CHR-ROM to fit. This drastically reduces the amount of modification necessary. Still, many of these images contain a 512-byte trainer that is loaded into PRG-RAM at $7000 if the game does not use battery-backed RAM, otherwise the trainer is loaded to $5D00 to not interfere with the save data.
| | The [[iNES]] header may specify a [[INES#Trainer|512-byte trainer]] (corresponding to [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Super_Magic_Card_disks|Doctor Header file]]'s byte $0 bit 6 being set). The trainer must be loaded to an address originally denoted by the [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Super_Magic_Card_disks|Doctor Header file]]'s byte $2, and is here denoted by the NES 2.0 submapper. In its presence, instead of jumping to the game's reset vector on a hard reset, trainer offset +$000 must be JMPed to. |
| | Submapper Trainer load address |
| | 0 $7000 |
| | 1 $5D00 |
| | 2 $5E00 |
| | 3 $5F00 |
|
| |
|
| =Banks=
| | Battery-saving of WRAM content is not supported by any Magic Card model. Hard-resetting a game while restoring previously-saved WRAM content in emulators interferes with the correct operation of the trainer's program. |
| * CPU $8000-$9FFF: 8 KiB PRG-ROM bank, switchable via register $4504
| |
| * CPU $A000-$BFFF: 8 KiB PRG-ROM bank, switchable via register $4505
| |
| * CPU $C000-$DFFF: 8 KiB PRG-ROM bank, switchable via register $4506
| |
| * CPU $E000-$FFFF: 8 KiB PRG-ROM bank, switchable via register $4507
| |
| * PPU $0000-$03FF: 1 KiB CHR-RAM bank, switchable via register $4510
| |
| * PPU $0400-$07FF: 1 KiB CHR-RAM bank, switchable via register $4511
| |
| * PPU $0800-$0BFF: 1 KiB CHR-RAM bank, switchable via register $4512
| |
| * PPU $0C00-$0FFF: 1 KiB CHR-RAM bank, switchable via register $4513
| |
| * PPU $1000-$13FF: 1 KiB CHR-RAM bank, switchable via register $4514
| |
| * PPU $1400-$17FF: 1 KiB CHR-RAM bank, switchable via register $4515
| |
| * PPU $1800-$1BFF: 1 KiB CHR-RAM bank, switchable via register $4516
| |
| * PPU $1C00-$1FFF: 1 KiB CHR-RAM bank, switchable via register $4517
| |
| | |
| =Registers=
| |
| ==Mirroring ($42FC-$42FF)==
| |
| A~FEDC BA98 7654 3210 D~7654 3210
| |
| ------------------- ---------
| |
| 0100 0010 1111 11.M ...M ....
| |
| +-------+------ Set nametable mirroring type
| |
| 0: One-screen, page 0
| |
| 1: One-screen, page 1
| |
| 2: Vertical
| |
| 3: Horizontal
| |
| | |
| ==Copier Configuration Register ($4500)==
| |
| D~7654 3210
| |
| ---------
| |
| MMWW IPPP
| |
| |||| |+++- PPU Mode. Set by the copier BIOS, games assume it to be 7.
| |
| |||| +---- IRQ source select
| |
| |||| 0: M2 rise
| |
| |||| 1: PA12 rise (unfiltered, e.g. 8 rises per scanline)
| |
| ||++------ SRAM mode at $6000-$7FFF. Set by the copier BIOS, games assume it to be 0.
| |
| ++-------- Copier mode. Set by the copier BIOS, games assume it to be 1.
| |
| | |
| ==IRQ Disable ($4501)==
| |
| Acknowledges and disables the IRQ counter.
| |
| | |
| ==IRQ Counter Low Byte ($4502)==
| |
| This is the low byte of a '''15-bit''' (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing
| |
| to this register also acknowledges the IRQ.
| |
| | |
| ==IRQ Counter High Byte ($4503)==
| |
| This is the high byte of a '''15-bit''' (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing
| |
| to this register also acknowledges and enables the IRQ.
| |
| | |
| ==PRG-ROM Bank registers ($4504-$4507)==
| |
| * $4504: Set 8 KiB PRG-ROM bank at CPU $8000-$9FFF
| |
| * $4505: Set 8 KiB PRG-ROM bank at CPU $A000-$BFFF
| |
| * $4506: Set 8 KiB PRG-ROM bank at CPU $C000-$DFFF
| |
| * $4507: Set 8 KiB PRG-ROM bank at CPU $E000-$FFFF
| |
| | |
| ==CHR-RAM Bank registers ($4510-$4517)==
| |
| * $4510: Set 1 KiB PRG-ROM bank at PPU $0000-$03FF
| |
| * $4511: Set 1 KiB PRG-ROM bank at PPU $0400-$07FF
| |
| * $4512: Set 1 KiB PRG-ROM bank at PPU $0800-$0BFF
| |
| * $4513: Set 1 KiB PRG-ROM bank at PPU $0C00-$0FFF
| |
| * $4514: Set 1 KiB PRG-ROM bank at PPU $1000-$13FF
| |
| * $4515: Set 1 KiB PRG-ROM bank at PPU $1400-$17FF
| |
| * $4516: Set 1 KiB PRG-ROM bank at PPU $1800-$1BFF
| |
| * $4517: Set 1 KiB PRG-ROM bank at PPU $1C00-$1FFF
| |
| | |
| =Notes=
| |
| * Before control is transferred to the game's Reset handler vectored at $FFFC, the copier BIOS issues a JSR to the Trainer's Init routine, if present. This call is necessary to properly set up initial CHR-RAM content and bankswitching registers. A few games also set up a table with IRQ counter values. Unlike [[INES Mapper 006]], the location of this Init routine varies between games. If a game has battery-backed RAM, this Init routine is always at $5D00; otherwise it can be at either $7000 or $7003, with the correct one detectable only via heuristics. $7003 seems to be correct unless the value at $7000 is $6C (indicating an indirect JMP), or both $7000 and $7003 contain the value $4C (JMP) ''and'' the jump offset at $7001 is lower than the jump offset at $7004.
| |
| * The FFE hack of ''Doki! Doki! Yuenchi'' has a graphical glitch during the introduction: the audience moves horizontally, caused by the IRQ handler writing an uninitialized Y register to $2005 that should be zero.
| |
iNES Mapper 017 denotes ROM images that have been extracted from disk images for the Front Fareast Super Magic Card RAM cartridge. They represent games whose Doctor Header file denotes a Super Magic Card disk (byte $0 bit 7 set, byte $7=$AA). Refer to the Super Magic Card article for details on bankswitching. The Super Magic Card's registers are initialized to:
; Play mode, WRAM bank 0, 1 KiB CHR mode enabled
$4500 = $47
; PRG memory write-protected, two-screen mirroring
$42FF = $20 | (verticalMirroring? 0x00: 0x10)
; 4M banking mode enabled
$43FC = $00
; Initial PRG register content
$4504 = Number of 8 KiB PRG banks -4
$4505 = Number of 8 KiB PRG banks -3
$4506 = Number of 8 KiB PRG banks -2
$4507 = Number of 8 KiB PRG banks -1 (originally Doctor Header file byte $5)
The iNES header may specify a 512-byte trainer (corresponding to Doctor Header file's byte $0 bit 6 being set). The trainer must be loaded to an address originally denoted by the Doctor Header file's byte $2, and is here denoted by the NES 2.0 submapper. In its presence, instead of jumping to the game's reset vector on a hard reset, trainer offset +$000 must be JMPed to.
Submapper Trainer load address
0 $7000
1 $5D00
2 $5E00
3 $5F00
Battery-saving of WRAM content is not supported by any Magic Card model. Hard-resetting a game while restoring previously-saved WRAM content in emulators interferes with the correct operation of the trainer's program.
