INES Mapper 043: Difference between revisions

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(Add Mr. Mary 2 information from FCEUX source code.)
m (Mr Mary is by Bit Corp.)
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{{DEFAULTSORT:043}}[[Category:iNES Mappers]][[Category:FDS conversion mappers]][[Category:Mappers with cycle IRQs]]iNES Mapper 043 is used for two conversions of ''Super Mario Bros. 2'' (Japanese) from Famicom Disk System to ROM cartridge:
{{DEFAULTSORT:043}}[[Category:iNES Mappers]][[Category:FDS conversion mappers]][[Category:Mappers with cycle IRQs]]iNES Mapper 043 is used for two conversions of ''Super Mario Bros. 2'' (Japanese) from Famicom Disk System to ROM cartridge:
* Whirlwind Manu's second attempt (cartridge number LF36) at converting the game. Their first attempt (cartridge number LE10, [[NES 2.0 Mapper 304]]) [https://archive.org/details/youtube-M2-ovBQW978 hangs on real hardware] after completing level 4-4.  
* Whirlwind Manu's second attempt (cartridge number LF36) at converting the game. Their first attempt (cartridge number LE10, [[NES 2.0 Mapper 304]]) [https://archive.org/details/youtube-M2-ovBQW978 hangs on real hardware] after completing level 4-4.  
* A version named ''Mr. Mary 2'' by an unknown publisher.
* A version named ''Mr. Mary 2'' by BIT Corporation.
FCEUX manages to emulate both under the same iNES mapper number. Their UNIF board name is '''UNL-SMB2J''', along with several incompatible boards annoyingly all carrying the same UNIF MAPR.
FCEUX manages to emulate both under the same iNES mapper number. Their UNIF board name is '''UNL-SMB2J''', along with several incompatible boards annoyingly all carrying the same UNIF MAPR.



Revision as of 09:55, 21 April 2018

iNES Mapper 043 is used for two conversions of Super Mario Bros. 2 (Japanese) from Famicom Disk System to ROM cartridge:

  • Whirlwind Manu's second attempt (cartridge number LF36) at converting the game. Their first attempt (cartridge number LE10, NES 2.0 Mapper 304) hangs on real hardware after completing level 4-4.
  • A version named Mr. Mary 2 by BIT Corporation.

FCEUX manages to emulate both under the same iNES mapper number. Their UNIF board name is UNL-SMB2J, along with several incompatible boards annoyingly all carrying the same UNIF MAPR.

Banks

Whirlwind Manu LF36

  • CPU $5000-$5FFF: 4 KiB PRG-ROM bank, fixed to #16 or #17 depending on DIP switch setting (determines whether the title screen has the SMB2 logo or not)
  • CPU $6000-$7FFF: 8 KiB PRG-ROM bank, fixed to #2
  • CPU $8000-$9FFF: 8 KiB PRG-ROM bank, fixed to #1
  • CPU $A000-$BFFF: 8 KiB PRG-ROM bank, fixed to #0
  • CPU $C000-$DFFF: 8 KiB PRG-ROM bank, switchable
  • CPU $E000-$FFFF: 8 KiB PRG-ROM bank, fixed to #9
  • PPU $0000-$1FFF: unbanked 8 KiB CHR-ROM

Mr. Mary 2

  • CPU $5000-$5FFF: 4 KiB PRG-ROM bank, fixed to #16
  • CPU $6000-$7FFF: 8 KiB PRG-ROM bank, switchable to #2 or #0
  • CPU $8000-$9FFF: 8 KiB PRG-ROM bank, fixed to #1
  • CPU $A000-$BFFF: 8 KiB PRG-ROM bank, fixed to #0
  • CPU $C000-$DFFF: 8 KiB PRG-ROM bank, switchable
  • CPU $E000-$FFFF: 8 KiB PRG-ROM bank, switchable to #10/#9 or #8
  • PPU $0000-$1FFF: unbanked 8 KiB CHR-RAM

Registers

PRG Bank Select 1 ($4022)

Mask: probably $71FF

Bit 7654 3210
    ---------
    .... .CCC
          +++- Select 8 KiB PRG-ROM bank at CPU $C000-$DFFF.

The actual bank number is:

Value  Bank#
------------
0      4
1      3
2      5
3      3
4      6
5      3
6      7
7      3

PRG Bank Select 2 ($4120, Mr. Mary 2 only)

Mask: probably $71FF

Bit 7654 3210
    ---------
    .... ...I
            +- 0: CPU $6000-$7FFF to bank 2,
                  CPU $E000-$FFFF to bank 10 (128 KiB ROM image)/9 (80 KiB ROM image)
               1: CPU $6000-$7FFF to bank 0,
                  CPU $E000-$FFFF to bank 8

FCEUX' source code claims that the actual hardware switches $E000-$FFFF to bank 10, used with an original 128 KiB ROM image, and that CaH4e3's released iNES ROM image of the game removes repeated banks to yield an 80 KiB ROM image that needs to switch to bank 9 instead.

IRQ Control ($4122/$8122)

Mask: probably $F1FF

Bit 7654 3210
    ---------
    .... ...I
            +- 0: Acknowledge and disable IRQ, reset counter
               1: Enable IRQ

When enabled, the 12-bit IRQ counter increases on every M2 cycle until it overflows, upon which an IRQ is fired.