INES Mapper 052: Difference between revisions

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[[Category:iNES Mappers|052]][[Category:MMC3-like mappers|052]][[Category:Multicart mappers|052]]
{{DEFAULTSORT:052}}[[Category:iNES Mappers]][[Category:MMC3-like mappers]][[Category:Multicart mappers]]'''iNES Mapper 052''' denotes the '''Realtec 8213''' and similar [[MMC3]]-based multicart circuit boards.
==Outer Bank Register ($6000-$7FFF, write)==
D~[LTCc SBPp]
    |||| ||++-- PRG A18..A17
    |||| |+---- PRG/CHR A19
    |||| +----- PRG A17 mode: 0=from MMC3, 1=from p
    ||++------- CHR A18..A17
    |+--------- CHR A17 mode: 0=from MMC3, 1=from c
    +---------- 1=Lock Outer Bank register until next reset
Value on reset: $00
The MMC3's WRAM interface must be enabled and writeable in [[MMC3#PRG RAM protect ($A001-$BFFF, odd)|MMC3 register $A001]]. The Outer Bank Register overlaps any actual PRG RAM that may be present.


These notes were updated on 2013-11-19 in response to [http://forums.nesdev.org/viewtopic.php?f=9&t=10703 this thread] on the forum.
==Mixed CHR ROM/CHR RAM variants==
Nestopia Plus! has defined '''Submapper 13''' to denote a PCB variant with 512 KiB of each PRG ROM and CHR ROM that can switch between regular CHR ROM and 8 KiB unbanked CHR RAM. CHR RAM is selected when PRG A17 and PRG A18 are both =1.


[[iNES Mapper 052]], like several other multicart mappers, supplements the [[MMC3]]'s RAM with a single register for switching between unmodified MMC3-compatible games.
Nestopia Plus! further uses Submapper 13 to denote the ''(AB-128) Well 8-in-1'' multicart with 1 MiB of each PRG ROM and CHR ROM, which is incompatible to the above definition, and which is hereby reassigned to '''Submapper 14'''. Its actual PCB name is '''AB892''', and its Outer Bank Register has the following form:


  Registers:
  D~[LTRc SBBp]
  ---------------------------
    |||| |||+-- PRG A18..A17
 
    |||| |++--- PRG/CHR A19..A18
    $6000-7FFF: [WMCC SBPP] Multicart reg
    |||| +----- PRG A17 mode: 0=from MMC3, 1=from p
      P = PRG Block (bits 1,0)
     |||+------- CHR A17
          = PRG A18 and A17
    ||+-------- 0=CHR-ROM, 1=CHR RAM
      B = CHR+PRG Block Select bit (PRG and CHR bit 2)
    |+--------- CHR A17 mode: 0=from MMC3, 1=from c
          = CHR and PRG A19
    +---------- 1=Lock Outer Bank register until next reset
      S = PRG Block size (0=256k  1=128k)
          = 0=PRG A17 comes from MMC3 1=A17 comes from this register
      C = CHR Block (bits 1,0)
          = CHR A18 and A17
      M = CHR Block size (0=256k  1=128k)
          = 0=CHR A17 comes from MMC3  1=A17 comes from this register
      W = 1=Disable multicart register and enable RAM
          0=allow further writes to multicart register
 
     $8000-FFFF:  Same as MMC3 for selected block
 
  This register can only be written to if PRG-RAM is enabled and writable (see $A001).
 
  PRG Setup:
  ---------------------------
 
    'S'    PRG-AND    PRG-OR
    ------------------------
      0       $1F    %BP0 0000
      1      $0F    %BPP 0000
 
  'B' and 'P' bits make a 3-bit value used as PRG-OR (left shift 4).  When 'S' is clear, the low bit of that
  value is forced to 0.
 
  PRG swapping behaves just like a normal MMC3 within this selected block
 
  CHR Setup:
  ---------------------------
 
    'M'    CHR-AND    CHR-OR
    ------------------------
      0       $FF    %BC 0000 0000
      1       $7F    %BC C000 0000
 
  'B' and 'C' bits make a 3-bit value used as CHR-OR (left shift 7).  When 'M' is clear, the low bit of
  that value is forced to 0.
 
  CHR swapping behaves just like a normal MMC3 within this selected block
 
  Powerup and Reset:
  ---------------------------
 
  $6000 set to 0 on reset and powerup.


The multicart register here can be implemented using two ICs: a 74273 (8 bit latch with asynchronous clear) and a 74153 (used as two independent one-of-two multiplexers). The 74273's /CLEAR input should be connected to something like
At least one cart (AB-134) re-uses this PCB but leaves the CHR RAM spot unpopulated, still using the combined bit for PRG/CHR A18, but rendering the "R" bit 5 meaningless. The correct NES 2.0 header for this would be submapper 14 but with zero CHR RAM.


  CPU M2 or CPU A0 --|>|--+-+-- /CLEAR
== See also ==
                          | |
* [http://nesdev.org/Mari7in1.txt "Mario Party" 7 in 1] by The Mad Dumper.
                          R C
* [http://forums.nesdev.org/viewtopic.php?f=9&t=10703 Forum thread] about mapper 052 by FARID
                          | |
                        gnd gnd
* Diode: 1N914 or any other small signal diode
* Resistor: approximately 10kΩ
* Capacitor: approximately 1nF

Latest revision as of 18:15, 30 November 2023

iNES Mapper 052 denotes the Realtec 8213 and similar MMC3-based multicart circuit boards.

Outer Bank Register ($6000-$7FFF, write)

D~[LTCc SBPp]
   |||| ||++-- PRG A18..A17
   |||| |+---- PRG/CHR A19
   |||| +----- PRG A17 mode: 0=from MMC3, 1=from p
   ||++------- CHR A18..A17
   |+--------- CHR A17 mode: 0=from MMC3, 1=from c
   +---------- 1=Lock Outer Bank register until next reset
Value on reset: $00

The MMC3's WRAM interface must be enabled and writeable in MMC3 register $A001. The Outer Bank Register overlaps any actual PRG RAM that may be present.

Mixed CHR ROM/CHR RAM variants

Nestopia Plus! has defined Submapper 13 to denote a PCB variant with 512 KiB of each PRG ROM and CHR ROM that can switch between regular CHR ROM and 8 KiB unbanked CHR RAM. CHR RAM is selected when PRG A17 and PRG A18 are both =1.

Nestopia Plus! further uses Submapper 13 to denote the (AB-128) Well 8-in-1 multicart with 1 MiB of each PRG ROM and CHR ROM, which is incompatible to the above definition, and which is hereby reassigned to Submapper 14. Its actual PCB name is AB892, and its Outer Bank Register has the following form: 

D~[LTRc SBBp]
   |||| |||+-- PRG A18..A17
   |||| |++--- PRG/CHR A19..A18
   |||| +----- PRG A17 mode: 0=from MMC3, 1=from p
   |||+------- CHR A17
   ||+-------- 0=CHR-ROM, 1=CHR RAM
   |+--------- CHR A17 mode: 0=from MMC3, 1=from c
   +---------- 1=Lock Outer Bank register until next reset

At least one cart (AB-134) re-uses this PCB but leaves the CHR RAM spot unpopulated, still using the combined bit for PRG/CHR A18, but rendering the "R" bit 5 meaningless. The correct NES 2.0 header for this would be submapper 14 but with zero CHR RAM.

See also

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