INES Mapper 095

What's written below is suspect, because the Namco 108 mapper does not have C or P bits, and sacrificing 32kB of CHR ROM just for the TxSROM-like ability to swap between 1ScA/1ScB/horizontal mirroring seems like a weird tradeoff.

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Dragon Buster (J) needs nametable rewiring to be emulated (based on bit 5 of the CHR regs) in order to work. The special description here for C and P bits is redundant, although reasonable from a certain less than completely synthesized point of view, as the result of MMC3's C mode bit is to yield CHR R0 and R1 as described in disch's doc when cleared and R2-5 when set. Therefore, this board must be a normal MMC3 but rewiring bit 5 of CHR to the nametable control.

Here's another way of looking at it. This game only has 32K of CHR, so they repurposed the next CHR mapping bit to be nametable control. Why not?

We should be able to rewrite this documentation to mention only the CHR->nametable bit wiring.

 Here are Disch's original notes:
 ========================
 =  Mapper 095          =
 ========================
 
 aka
 --------------------------
 MMC3  (modified)
 
 
 Example Game:
 --------------------------
 Dragon Buster (J)
 
 
 Notes:
 ---------------------------
 This mapper is a modified MMC3.  It behaves exactly like your normal MMC3, only mirroring is handled
 differently.  For details on MMC3, refer to mapper 004.
 
 
 Regs:
 ---------------------------
 
 $8000:  [CP.. .AAA]
    C = CHR Mode
    P = PRG Mode
    A = Address for $8001
 
 
 This register operates exactly like it does on your normal MMC3.  It is mentioned here because the 'C' bit
 has another usage for mirroring.
 
 
 
 The normal mirroring reg ($A000) is totally ignored, and the CHR regs select nametables:
 
 When 'C' is set:
    [ R:2 ][ R:3 ]
    [ R:4 ][ R:5 ]
 
 When 'C' is clear:
    [ R:0 ][ R:0 ]
    [ R:1 ][ R:1 ]
 
 
 For mirroring, only bit 5 of the CHR regs is significant.  Bit 5 of the appropriate reg selects either NTA or
 NTB.