INES Mapper 157

iNES Mapper 157 is used for games using the Datach Joint ROM system. The Datach main unit is a device for insertion into the Famicom's cartridge port that provides a barcode scanner, and that accepts its own custom game cartridges. It contains an internal 256-byte serial EEPROM (24C02) that is shared among all Datach games.

One game, Battle Rush: Build up Robot Tournament, has an additional external 128-byte serial EEPROM (24C01) on the game cartridge. As part of that game's functionality is to transfer save data between the Datach main unit's EEPROM and the game cartridge's EEPROM, emulators should save each EEPROM's data to separate files, one for the main unit's EEPROM, and one for the game cartridge's EEPROM.

The NES 2.0 header's PRG-NVRAM field will only denote whether the game cartridge has an additional 128-byte serial EEPROM (byte 10 value 0x10) or not (byte 10 value 0x00). The Datach main unit's serial EEPROM is not included in the NES 2.0 header's PRG-NVRAM field, as that EEPROM is not part of the game cartridge, but instead shared among all games using this mapper.

Game List

Name	External EEPROM	NES 2.0 Byte 10
Battle Rush: Build up Robot Tournament	24C01	0x10
Crayon Shin-chan: Ora to Poi Poi	-	0x00
Dragon Ball Z: Gekitou Tenkaichi Budoukai	-	0x00
J-League Super Top Players	-	0x00
SD Gundam Wars	-	0x00
Ultraman Club: Spokon Fight!!	-	0x00
Yuu Yuu Hakusho - Bakutou Ankoku Bujutsu-kai	-	0x00

Banks

• CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
• CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last bank
• PPU $0000-$1FFF: 8 KiB unbanked CHR-RAM

Registers

Read Serial EEPROM/Barcode ($6000-$7FFF read)

Mask: $E000

7  bit  0
---- ----
xxxE Bxxx
|||| ||||
+++|-|+++- Open bus
   | +---- Serial data out from Barcode scanner
   +------ Data out from I²C EEPROMs

• If there is both an internal and an external EEPROM, the Data out from both EEPROMs is ANDed (open drain circuit).
• Please see the FCEUX source code for a description of the barcode scanner's serial protocol.

External EEPROM Clock ($8000-$8003 write)

Mask: $800F

7  bit  0
---- ----
xxxx Cxxx
     |   
     +----- External EEPROM's I²C SCL

• CHR A13 OUT is provided on the subcartridge header, and is used in Battle Rush as an external I²C clock.
• PPU rendering must either be disabled during traffic to the external EEPROM, or the same value must be written to all four registers.
• Because the ASIC's PA12 and PA13 inputs are grounded, only registers $8000-$8003 instead of $8000-$8007 are relevant.
• No CHR banking is available.

PRG-ROM Bank Select ($8008 write)

Mask: $800F

7  bit  0
---- ----
.... PPPP
     ||||
     ++++-- Select 16 KiB PRG-ROM bank at CPU $8000-$BFFF   

Nametable Mirroring Type Select ($8009 write)

Mask: $800F

7  bit  0
---- ----
.... ..MM
       ||
       ++-- Select nametable mirroring type
             0: Vertical
             1: Horizontal
             2: One-screen, page 0
             3: One-screen, page 1

IRQ Control ($800A write)

Mask: $800F

7  bit  0
---- ----
.... ...C
        |
        +-- IRQ counter control
             0: Counting disabled
             1: Counting enabled

• Writing to this register acknowledges a pending IRQ, and copies the latch to the actual counter.
• If a write to this register enables counting while the counter is holding a value of zero, an IRQ is generated immediately.

IRQ Latch ($800B-$800C write)

Mask: $800F

   $C         $B
7  bit  0  7  bit  0
---- ----  ---- ----
CCCC CCCC  CCCC CCCC
|||| ||||  |||| ||||
++++-++++--++++-++++-- Counter value (little-endian)

• If counting is enabled, the counter decreases on every M2 cycle. When it holds a value of zero, an IRQ is generated.
• These registers modify a latch that will only be copied to the actual counter when register $xxxA is written to.

EEPROM Control ($800D write)

Mask: $800F

7  bit  0
---- ----
RDC. ....
|||
||+-------- Internal EEPROM's I²C SCL
|+--------- Both EEPROM's I²C SDA
+---------- Both EEPROM's Direction bit (1=Enable Read)

• Please refer to generic I²C tutorials and the 24C01/24C02 datasheets on how to operate or emulate this register correctly.
• The device address of the internal 24C02 EEPROM is set to 000b (with the highest "device type" bits being 1010b), whereas the external 24C01 EEPROM responds to any I²C start condition. It is for this reason that there are two clock lines to address each EEPROM separately.
• Note that while the 24C02 serializes data bits from MSB to LSB (i.e. first bit 7 of any byte, then 6..0), the 24C01 serializes data bits from LSB to MSB instead.