INES Mapper 173: Difference between revisions

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INES Mapper 173 is used to denote an unmarked board used by the original Idea-Tek releases (cartridge codes ET-xx) of several of their games:
INES Mapper 173 is used to denote an unmarked board used by the original Idea-Tek releases (cartridge codes ET-xx) of several of their games:


* ''Puzzle'' (ET-01)
* ''Puzzle'' (ET.01)
* ''小瑪琍'' (Xiǎo Mǎlí) (Nei-Hu and Idea-Tek releases, with identical cartridge shell and label) (ET-02)
* ''小瑪琍'' (Xiǎo Mǎlí) (Nei-Hu and Idea-Tek releases, with identical cartridge shell and label) (ET.02)
* ''F-15 City War'' (ET-03)
* ''F-15 City War'' (ET.03)
* ''撲克精靈'' (Poker Jīnglíng) (ET-04)
* ''撲克精靈'' (Poker Jīnglíng) (ET.04)
* ''戰國四川省'' (Zhànguó Sìchuān Shěng) (ET-05), developed by Computer & Entertainment
* ''戰國四川省'' (Zhànguó Sìchuān Shěng) (ET.05), developed by Computer & Entertainment


==Banks==
==Banks==

Revision as of 19:54, 16 February 2018

INES Mapper 173 is used to denote an unmarked board used by the original Idea-Tek releases (cartridge codes ET-xx) of several of their games:

  • Puzzle (ET.01)
  • 小瑪琍 (Xiǎo Mǎlí) (Nei-Hu and Idea-Tek releases, with identical cartridge shell and label) (ET.02)
  • F-15 City War (ET.03)
  • 撲克精靈 (Poker Jīnglíng) (ET.04)
  • 戰國四川省 (Zhànguó Sìchuān Shěng) (ET.05), developed by Computer & Entertainment

Banks

  • PPU $0000-$1FFF: 8 KB switchable CHR ROM bank

Registers

Mapper 173 uses a custom IC (real number 05-00002-010, fake marking "ITC20V8-10LP", falsely suggesting a particular type of programmable logic) serving as a latch, adder and inverter. There are five registers: Input (4 bits), Output (4 bits), Register (4 bits), Mode (1 bit) and Invert (1 bit).

Mask: $E103
Read $4100-$4103: [.... RRRR]: Read Register. Bit 3 is inverted if Invert==1. Bits 4-7 are open bus.
Write $4100: When Mode==0: Bits 0-3 of Register := Input, bits 0-2 being inverted if Invert==1.
             When Mode==1: Bits 0-2 of Register incremented by one, bit 3 unaffected.
Write $4101: Invert := Written value bit 0.
Write $4102: Input := Written value bits 0-3.
Write $4103: Mode := Written value bit 0.
Write $8000-$FFFF: Output := Register; written value is ignored.

In Mapper 173, bit 0 of the 8 KiB CHR ROM bank number (CHR A13) comes from Output bit 0, while bit 1 of the 8 KiB CHR ROM bank number (CHR A14) is the inverted value of the Invert register:

8 KiB CHR-ROM bank number := (Output &1) | (~Invert <<1);

Games therefore set Invert (writing $FF or $01 to $4101) to choose CHR banks 0 and 1, and clear Invert (writing $00 to $4101) to choose CHR banks 2 and 3. 小瑪琍 (Xiǎo Mǎlí) uses this for copy-protection purposes, having 32 KiB of CHR-ROM with the first 16 KiB empty, always clearing Invert and writing $0E/$0C/$08/$06/$04/$02/$00 to Input and expecting CHR A14 to remain 1. Games will also check the lower nibble of $4100 for the correct value after several increment and inversion operations, again as a copy-protection measure.

Errata

  • 麻将方块 (Mahjong Block) (TXC re-release, headerless CRC32 0ACFC3CD) is commonly set to mapper 173, but since it expects Output bit 1 to select CHR A14, it actually uses INES Mapper 132.
  • 撲克精靈 (Poker Jīnglíng) writes the actual 8 KiB bank number to $8000 to copy Register into Output, making it potentially CNROM-compatible. It will not run as Mapper 3 on emulators that emulate bus conflicts (such as FCEUX) though, nor will it run on an actual Nintendo CNROM board, for the same reason.
  • Rad Racket - Deluxe Tennis II (TXC release, MGC-011) uses a TXC 01-22111-100 (INES Mapper 132) board but sets/clears Invert for 8 KiB CHR-ROM banks 0 and 1/2 and 3, making it compatible with Mapper 173 as well.
  • 戰國四川省 (Zhànguó Sìchuān Shěng, original version of AVE's Tiles of Fate) is set to Mapper 132 in GoodNES 3.23b. That ROM image is actually a mapper hack with the PRG-ROM code unmodified but the CHR-ROM banks rearranged to work as Mapper 132; the correct mapper is INES Mapper 173.

Similar Mappers

  • INES Mapper 173 is similar to INES Mapper 132 with only 32 KiB PRG-ROM except that Mapper 132 connects CHR A14 to Output bit 1 rather than the inverse of the Invert bit.

See also

PCB image