INES Mapper 206: Difference between revisions

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[[Category:iNES Mappers|206]][[Category:MMC3-like mappers|206]][[iNES Mapper 206]] is a stripped-down version of [[MMC3]] used by Tengen and Namco.
[[Category:iNES Mappers|206]][[Category:MMC3-like mappers|206]][[Category:in NesCartDB|206]]
[[iNES Mapper 206]] is a stripped-down version of [[MMC3]] used by Tengen and Namco.
Chips used include "Tengen MIMIC-1" and "[[Namcot 108 family pinout|Namcot 118]]", and the boards made by Nintendo of America that used this mapper are NES-[[DxROM]].
Chips used include "Tengen MIMIC-1" and "[[Namcot 108 family pinout|Namcot 118]]", and the boards made by Nintendo of America that used this mapper are NES-[[DxROM]].
Many ROMS using this mapper are incorrectly listed as using MMC3, but will usually work if emulated with MMC3, and the mirroring is correct, as if they were on a [[TxROM|TEROM or TFROM board]].
Many ROMS using this mapper are incorrectly listed as using MMC3, but will usually work if emulated with MMC3, and the mirroring is correct, as if they were on a [[TxROM|TEROM or TFROM board]].

Revision as of 03:42, 29 July 2012

iNES Mapper 206 is a stripped-down version of MMC3 used by Tengen and Namco. Chips used include "Tengen MIMIC-1" and "Namcot 118", and the boards made by Nintendo of America that used this mapper are NES-DxROM. Many ROMS using this mapper are incorrectly listed as using MMC3, but will usually work if emulated with MMC3, and the mirroring is correct, as if they were on a TEROM or TFROM board.

Compared to MMC3:

  • There are no IRQs
  • There is no WRAM support
  • PRG always has the last two 8k banks fixed to the end.
  • CHR always gives the left pattern table (0000-0FFF) the two 2k banks, and the right pattern table (1000-1FFF) the four 1k banks.
  • Mirroring is hardwired, one game uses 4-screen mirroring (Gauntlet).
  • CHR size limit is 64k, PRG size limit is 128k.

Registers:

  • $8000: 00000xxx - Select which internal register gets written by $8001
  • $8001: 00xxxxxx - Value written to the internal register. PRG registers use only 4 bits.

Internal registers:

  • 0, 1: 2k CHR banks at 0000, 0800. Least significant bit is ignored.
  • 2, 3, 4, 5: 1k CHR banks at 1000, 1400, 1800, 1C00.
  • 6, 7: 8k PRG banks at 8000, A000.

Variants

Mapper 76 increases CHR to 128kB by inflating the 1k CHR banks to 2k and making the originally-2k banks inaccessible.

Mappers 88 and 154 increase CHR to 128kB by connecting PPU's A12 line to the CHR ROM's A16 line, making tiles in $0000 and $1000 come from disjoint sections of ROM.

Mapper 154 additionally adds mapper-controlled one-screen mirroring.

Mapper 95 is like this mapper except that CHR A15 controls CIRAM A10, much as CHR A17 controls CIRAM A10 in TxSROM.

References

  • FCEUX source code