INES Mapper 243: Difference between revisions
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NewRisingSun (talk | contribs) (No readable solder pad on SA-020A.) |
(→Register Data ($4101, read/write): call out that all registers can be fully read and written. fix typo in R4) |
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* CPU $8000-$FFFF: switchable 32 KiB PRG-ROM bank | * CPU $8000-$FFFF: switchable 32 KiB PRG-ROM bank | ||
* PPU $0000-$1FFF: switchable 8 KiB CHR-ROM bank | * PPU $0000-$1FFF: switchable 8 KiB CHR-ROM bank | ||
* Nametable mirroring: switchable H/V/L | * Nametable mirroring: switchable H/V/Vertically-flipped L/One-screen | ||
=Registers= | =Registers= | ||
| Line 16: | Line 16: | ||
+++- Select register number (Rx) | +++- Select register number (Rx) | ||
==Register Data ($4101, write)== | ==Register Data ($4101, read/write)== | ||
Mask: $C101 | Mask: $C101 | ||
| Line 27: | Line 27: | ||
--------- | --------- | ||
.... ...A R2: CHR A13 | .... ...A R2: CHR A13 | ||
.... ... | .... ...B R4: CHR A14 | ||
.... ..PP R5: PRG A16..A15 | .... ..PP R5: PRG A16..A15 | ||
.... ..DC R6: CHR A16..A15 | .... ..DC R6: CHR A16..A15 | ||
... .MM. R7: Nametable mirroring | ... .MM. R7: Nametable mirroring | ||
0: | 0: S0-S0-S0-S1 (lower right unique, or vertically-flipped L) | ||
1: Horizontal | 1: Horizontal | ||
2: | 2: Vertical | ||
3: Single-screen | 3: Single-screen, page 1 | ||
Registers 0 | Registers 0, 1, and 3 have no external effect. All three bits in all eight registers are fully implemented and can be read from and written to. | ||
=Errata= | =Errata= | ||
The '''SA-150''' PCB, denoted by [[INES Mapper 150]], connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits. | The '''SA-150''' PCB, denoted by [[INES Mapper 150]], connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits. | ||
Latest revision as of 19:21, 14 December 2019
iNES Mapper 243 denotes the Sachen SA-020A circuit board. Using an eight-register ASIC with a fake "74LS374N" marking, it supports up to 128 KiB PRG-ROM, and 128 KiB of CHR-ROM. It is used for only one game, 美女拳 - Honey Peach (SA-006).
Banks
- CPU $8000-$FFFF: switchable 32 KiB PRG-ROM bank
- PPU $0000-$1FFF: switchable 8 KiB CHR-ROM bank
- Nametable mirroring: switchable H/V/Vertically-flipped L/One-screen
Registers
Register Index ($4100, write)
Mask: $C101
D~7654 3210
---------
.... .RRR
+++- Select register number (Rx)
Register Data ($4101, read/write)
Mask: $C101
D~7654 3210
---------
.... .RRR
+++- Register data
D~7654 3210
---------
.... ...A R2: CHR A13
.... ...B R4: CHR A14
.... ..PP R5: PRG A16..A15
.... ..DC R6: CHR A16..A15
... .MM. R7: Nametable mirroring
0: S0-S0-S0-S1 (lower right unique, or vertically-flipped L)
1: Horizontal
2: Vertical
3: Single-screen, page 1
Registers 0, 1, and 3 have no external effect. All three bits in all eight registers are fully implemented and can be read from and written to.
Errata
The SA-150 PCB, denoted by INES Mapper 150, connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits.
