INES Mapper 245: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
No edit summary
(Rewrite)
 
(6 intermediate revisions by 3 users not shown)
Line 1: Line 1:
"Mapper 245 uses bit 2 of CHR Register 0 to select which 512KB bank of PRG ROM is seen. This increases the maximum PRG size up to 1024K.  CHR RAM is not bankable, but the top bit of $8000 will still switch the left and right pattern tables."
{{DEFAULTSORT:245}}[[Category:iNES Mappers]][[Category:MMC3-like mappers]][[Category:Mappers with CHR RAM]][[Category:Mappers with scanline IRQs]]
'''iNES Mapper 245''' denotes the Waixing '''F003''' circuit board. It mounts an [[MMC3]] clone with 8 KiB of battery-backed WRAM and 8 KiB of unbanked CHR-RAM, making it functionally similar to [[TNROM]]. Additionally however, in a similar fashion to [[SUROM]], the MMC3's CHR address outputs are repurposed as higher PRG address lines to extend the PRG address space from the MMC3's own 512 KiB to 1 MiB.


[[Category:iNES Mappers]]
Its features are used on a single game: "勇者斗恶龙 VII - Dragon Quest" (Yǒngzhě dòu è lóng VII - Dragon Quest), Waixing's Chinese translation of Dragon Quest IV. Waixing used that PCB however for other MMC3/CHR-RAM games with smaller PRG-ROM sizes as well, for which the board reduces to TNROM-like functionality.
  Here are Disch's original notes: 
 
  ========================
=Pin Connections=
  = Mapper 245          =
  Normal MMC3 pin function  F003 pin function
  ========================
-------------------------------------------
 
PPU A12 ->                GND ->
 
-> CHR A10                none
  Example Games:
-> CHR A11                -> PRG A19
  --------------------------
-> CHR A12                none
  Chu Han Zheng Ba - The War Between Chu & Han
-> CHR A13                none
  Xing Ji Wu Shi - Super Fighter
-> CHR A14                none
  Yin He Shi Dai
-> CHR A15                none
  Yong Zhe Dou e Long - Dragon Quest VII (As)
-> CHR A16                none
  Dong Fang de Chuan Shuo - The Hyrule Fantasy
-> CHR A17                none
 
 
 
CHR-RAM's A10-A12 inputs are connected directly to PPU A10-A12; as a result, the MMC3's CHR bank registers have no effect at all on pattern tables. The MMC3's PPU A12 input is connected to GND, meaning that only MMC3 CHR bank registers 0/1 ($8000.7=0) or 2-5 ($8000.7=1) are functional. The MMC3's CHR A11 output is connected to the PRG-ROM chip's A19 input. This means that bit 1 (bit value $02) of the currently active MMC3 CHR bank register selects the 512 KiB PRG-ROM bank that applies to the entire CPU $8000-$FFFF address range.
  Notes:
 
  ---------------------------
=Registers=
  Another ?Chinese? MMC3 clone.  Very similar to your typical MMC3. For MMC3 info, see mapper 004.
$8001 when $8000=$x0: [.... ..B.]
 
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
  Register layout is identical to a typical MMC3.
          when PPU is rendering from BG or OBJ tiles $00-$7F
 
          and $8000.7=0
 
$8001 when $8000=$x1: [.... ..B.]
 
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
  CHR Setup:
          when PPU is rendering from BG or OBJ tiles $80-$FF
  ---------------------------
          and $8000.7=0
 
  CHR-RAM is not swappable.  When there is no CHR-ROM present, 8k CHR-RAM is fixed. However the CHR Mode bit
$8001 when $8000=$x2: [.... ..B.]
  ($8000.7) can still "flip" the left/right pattern tables.
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
 
          when PPU is rendering from BG or OBJ tiles $00-$3F
  Example:
          and $8000.7=1
 
$8001 when $8000=$x3: [.... ..B.]
                      $0000  $0400  $0800  $0C00  $1000  $1400  $1800  $1C00
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
                    +-------------------------------+-------------------------------+
          when PPU is rendering from BG or OBJ tiles $40-$7F
  CHR-RAM, Mode 0: |            { 0 }            |            { 1 }            |
          and $8000.7=1
                    +-------------------------------+-------------------------------+
$8001 when $8000=$x4: [.... ..B.]
  CHR-RAM, Mode 1: |            { 1 }            |            { 0 }            |
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
                    +---------------------------------------------------------------+
          when PPU is rendering from BG or OBJ tiles $80-$BF
  CHR-ROM:          |                          Typical MMC3                        |
          and $8000.7=1
                    +---------------------------------------------------------------+
  $8001 when $8000=$x5: [.... ..B.]
 
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
 
          when PPU is rendering from BG or OBJ tiles $C0-$FF
  PRG Setup:
          and $8000.7=1
  ---------------------------
 
 
Registers 0/1 or 2-5 must specify the same 512 KiB PRG-ROM bank, otherwise the bank would switch as the PPU is rendering. The only game using this mapper has boot code and reset vectors in both 512 KiB PRG halves, making the initial CHR register content irrelevant.
  PRG Setup is the same as a normal MMC3, although there's a PRG-AND of $3F, and games select a 512k Block with
  bit 1 of R:0. Pretty simple really:
 
    R:0:  [.... ..P.]
 
    'P'    PRG-AND    PRG-OR
  --------------------------
    0      $3F        $00
    1       $3F        $40
 
 
  R:0 remains the normal MMC3 CHR reg, as well. Although the game that uses it as a PRG block selector ("DQ7")
  uses CHR-RAM, so it is normally ignored.

Latest revision as of 17:31, 18 November 2020

iNES Mapper 245 denotes the Waixing F003 circuit board. It mounts an MMC3 clone with 8 KiB of battery-backed WRAM and 8 KiB of unbanked CHR-RAM, making it functionally similar to TNROM. Additionally however, in a similar fashion to SUROM, the MMC3's CHR address outputs are repurposed as higher PRG address lines to extend the PRG address space from the MMC3's own 512 KiB to 1 MiB.

Its features are used on a single game: "勇者斗恶龙 VII - Dragon Quest" (Yǒngzhě dòu è lóng VII - Dragon Quest), Waixing's Chinese translation of Dragon Quest IV. Waixing used that PCB however for other MMC3/CHR-RAM games with smaller PRG-ROM sizes as well, for which the board reduces to TNROM-like functionality.

Pin Connections

Normal MMC3 pin function  F003 pin function
-------------------------------------------
PPU A12 ->                GND ->
-> CHR A10                none
-> CHR A11                -> PRG A19
-> CHR A12                none
-> CHR A13                none
-> CHR A14                none
-> CHR A15                none
-> CHR A16                none
-> CHR A17                none

CHR-RAM's A10-A12 inputs are connected directly to PPU A10-A12; as a result, the MMC3's CHR bank registers have no effect at all on pattern tables. The MMC3's PPU A12 input is connected to GND, meaning that only MMC3 CHR bank registers 0/1 ($8000.7=0) or 2-5 ($8000.7=1) are functional. The MMC3's CHR A11 output is connected to the PRG-ROM chip's A19 input. This means that bit 1 (bit value $02) of the currently active MMC3 CHR bank register selects the 512 KiB PRG-ROM bank that applies to the entire CPU $8000-$FFFF address range.

Registers

$8001 when $8000=$x0: [.... ..B.]
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
          when PPU is rendering from BG or OBJ tiles $00-$7F
          and $8000.7=0
$8001 when $8000=$x1: [.... ..B.]
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
          when PPU is rendering from BG or OBJ tiles $80-$FF
          and $8000.7=0

$8001 when $8000=$x2: [.... ..B.]
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
          when PPU is rendering from BG or OBJ tiles $00-$3F
          and $8000.7=1
$8001 when $8000=$x3: [.... ..B.]
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
          when PPU is rendering from BG or OBJ tiles $40-$7F
          and $8000.7=1
$8001 when $8000=$x4: [.... ..B.]
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
          when PPU is rendering from BG or OBJ tiles $80-$BF
          and $8000.7=1
$8001 when $8000=$x5: [.... ..B.]
          Select 512 KiB PRG-ROM bank at CPU $8000-$FFFF
          when PPU is rendering from BG or OBJ tiles $C0-$FF
          and $8000.7=1

Registers 0/1 or 2-5 must specify the same 512 KiB PRG-ROM bank, otherwise the bank would switch as the PPU is rendering. The only game using this mapper has boot code and reset vectors in both 512 KiB PRG halves, making the initial CHR register content irrelevant.