MMC3 pinout: Difference between revisions

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Notes:
Notes:
*Both versions enables WRAM at $6000-$7fff at power up but protects them from writes
*Both versions enables WRAM at $6000-$7fff at power up but protects them from writes (during CPU write cycle to $6000-$7fff when WRAM is protected, WRAM !CE and WRAM CE are not asserted). When RAM is disabled, open bus behavior is observed.
(during CPU write cycle to $6000-$7fff when WRAM is protected, WRAM !CE and WRAM CE are not asserted).
*NC seems to be not connected internally in both versions (multimeter diode test does not show any conducting voltage between NC and any other pins)
When RAM is disabled, open bus behavior is observed.
*NC seems to be not connected internally in both versions (multimeter diode test
does not show any conducting voltage between NC and any other pins)
*First version is the one you can still buy nowadays (it has AX5202P marking).
*First version is the one you can still buy nowadays (it has AX5202P marking).
*Second version was found in at least one game - Doki Doki Yuuenchi bootleg (the chip
*Second version was found in at least one game - Doki Doki Yuuenchi bootleg (the chip does not have any markings)
does not have any markings)

Revision as of 17:50, 17 September 2017

Nintendo MMC3: 44-pin QFP (Canonically mapper 4)

                             / \
                            / O \
                    n/c -- /01 44\ -> CHR A16 (r)
           (r) CHR A10 <- /02   43\ -> CHR A11 (r)
          (n) PPU A12 -> /03     42\ -> PRG RAM /WE (w)
         (n) PPU A11 -> /04       41\ -> PRG RAM +CE (w)
        (n) PPU A10 -> /05         40\ -- GND
               GND -- /06         \ 39\ <- CPU D3 (nrw)
      (r) CHR A13 <- /07           \ 38\ <- CPU D2 (nrw)
     (r) CHR A14 <- /08         \  _\ 37\ <- CPU D4 (nrw)
    (r) CHR A12 <- /09         \ \|    36\ <- CPU D1 (nrw)
 (n) CIRAM A10 <- /10           \ \     35\ <- CPU D5 (nrw)
  (r) CHR A15 <- /11         \  _\    o  34\ <- CPU D0 (nrw)
  (r) CHR A17 <- \12       /\ \|         33/ <- CPU D6 (nrw)
      (n) /IRQ <- \13        \ \        32/ <- CPU A0 (nrw)
    (n) /ROMSEL -> \14   /    \        31/ <- CPU D7 (nrw)
             GND -- \15  |_   /       30/ -> PRG RAM /CE (w)
              n/c -- \16   |         29/ <- M2 (n)
           (n) R/W -> \17  |/       28/ -- GND
        (r) PRG A15 <- \18         27/ -- VCC
         (r) PRG A13 <- \19       26/ -> PRG /CE (r)
          (n) CPU A14 -> \20     25/ -> PRG A17 (r)
           (r) PRG A16 <- \21   24/ <- CPU A13 (n)
            (r) PRG A14 <- \22 23/ -> PRG A18 (r)
                            \ O /
                             \ /

01, 16: both officially no connection. sometimes shorted to pin 02, 15 respectively

Note the orientation of the text: "MMC3" when viewed upright specifies pin 1 is bottom face, leftmost.

Mappers 37 and 47 connect pins 42 and 30 to a 74161

iNES Mapper 118 connects pin 12 to CIRAM A10, and pin 10 is n/c.

iNES Mapper 119 connects pin 44 to a 7432 and to the CHR RAM's +CE pin.

Pirate versions (600 mil 40-pin DIP package)

            .--\/--.                                 .--\/--.               
      M2 -> |01  40| -- +5V           CPU !ROMSEL -> |01  40| -> WRAM !CE   
WRAM !CE <- |02  39| -- NC                PRG !CE <- |02  39| -- +5V        
  CPU D7 -> |03  38| -> PRG !CE          WRAM !WE <- |03  38| -> WRAM CE       
  CPU A0 -> |04  37| -> PRG A17           CPU A14 -> |04  37| <- CPU R/!W   
  CPU D6 -> |05  36| <- CPU A13           CPU A13 -> |05  36| -> PRG A13    
  CPU D0 -> |06  35| -> PRG A18            CPU A0 -> |06  35| -> PRG A14    
  CPU D5 -> |07  34| -> PRG A14                M2 -> |07  34| -> PRG A15    
  CPU D1 -> |08  33| -> PRG A16           PPU A12 -> |08  33| -> PRG A16    
  CPU D4 -> |09  32| <- CPU A14              !IRQ <- |09  32| -> PRG A17    
  CPU D2 -> |10  31| -> PRG A13         CIRAM A10 <- |10  31| -> PRG A18    
  CPU D3 -> |11  30| -> PRG A15           PPU A10 -> |11  30| -- NC         
 WRAM CE <- |12  29| <- CPU R/!W          PPU A11 -> |12  29| -> CHR A17    
WRAM !WE <- |13  28| <- CPU !ROMSEL        CPU D0 -> |13  28| -> CHR A16    
 CHR A11 <- |14  27| -> !IRQ               CPU D1 -> |14  27| -> CHR A15    
 CHR A16 <- |15  26| -> CHR A17            CPU D2 -> |15  26| -> CHR A14    
 CHR A10 <- |16  25| -> CHR A15            CPU D3 -> |16  25| -> CHR A13    
 PPU A12 -> |17  24| -> CIRAM A10          CPU D4 -> |17  24| -> CHR A12    
 PPU A11 -> |18  23| -> CHR A12            CPU D5 -> |18  23| -> CHR A11    
 PPU A10 -> |19  22| -> CHR A14            CPU D6 -> |19  22| -> CHR A10    
     GND -- |20  21| -> CHR A13               GND -- |20  21| <- CPU D7     
            `------'                                 `------'               
           AX5202P #1                             AX5202P #2 (NTDEC?)       

Notes:

  • Both versions enables WRAM at $6000-$7fff at power up but protects them from writes (during CPU write cycle to $6000-$7fff when WRAM is protected, WRAM !CE and WRAM CE are not asserted). When RAM is disabled, open bus behavior is observed.
  • NC seems to be not connected internally in both versions (multimeter diode test does not show any conducting voltage between NC and any other pins)
  • First version is the one you can still buy nowadays (it has AX5202P marking).
  • Second version was found in at least one game - Doki Doki Yuuenchi bootleg (the chip does not have any markings)