MMC5 pinout: Difference between revisions

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m (It's PPU /A13, not A13)
(new discoveries)
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                               (fr) PPU A1 -> / 6            95 \ -> CHR A1 *
                               (fr) PPU A1 -> / 6            95 \ -> CHR A1 *
                             (fr) PPU A2 -> / 7              94 \ -> CHR A0 *
                             (fr) PPU A2 -> / 7              94 \ -> CHR A0 *
                             (fr) PPU A3 -> / 8                93 \ -> (unknown output)
                             (fr) PPU A3 -> / 8                93 \ -> PRG RAM A15
                           (fr) PPU A4 -> / 9                  92 \ ?? (unknown)
                           (fr) PPU A4 -> / 9                  92 \ ?? (unknown input)
                           (fr) PPU A5 -> / 10                  91 \ <> PPU D7 (fr)
                           (fr) PPU A5 -> / 10                  91 \ <> PPU D7 (fr)
                         (fr) PPU A6 -> / 11                    90 \ <> PPU D6 (fr)
                         (fr) PPU A6 -> / 11                    90 \ <> PPU D6 (fr)
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                   (r) CHR A12 <- / 17                                84 \ <> PPU D0 (fr)
                   (r) CHR A12 <- / 17                                84 \ <> PPU D0 (fr)
                   (r) CHR A13 <- / 18                                  83 \ -> PRG RAM +CE
                   (r) CHR A13 <- / 18                                  83 \ -> PRG RAM +CE
                 (r) CHR A14 <- / 19                                    82 \ ?? (unknown)
                 (r) CHR A14 <- / 19                                    82 \ ?? (unknown input)
                 (r) CHR A15 <- / 20                                      81 \ ?? (unknown)
                 (r) CHR A15 <- / 20                                      81 \ ?? (unknown input)
               (r) CHR A16 <- / 21                                            \
               (r) CHR A16 <- / 21                                            \
               (r) CHR A17 <- / 22                                            /
               (r) CHR A17 <- / 22                                            /
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           (f) PPU A11 -> / 26              Nintendo MMC5              77 / <- CPU R/W (f)
           (f) PPU A11 -> / 26              Nintendo MMC5              77 / <- CPU R/W (f)
         (f) PPU A12 -> / 27      Package QFP-100, 0.65mm pitch      76 / -> PRG RAM /WE (R)
         (f) PPU A12 -> / 27      Package QFP-100, 0.65mm pitch      76 / -> PRG RAM /WE (R)
       (f) PPU /A13 -> / 28                                          75 / -> (unknown RAM control signal) (R)
       (f) PPU /A13 -> / 28                                          75 / -> PRG RAM /CE (RAM0/CE & RAM1/CE)
        (unknown) ?? / 29                                          74 / -> PRG /CE (r)
  (unknown input) ?? / 29                                          74 / -> PRG /CE (r)
        (unknown) ?? / 30                                          73 / -> (unknown output)
  (unknown input) ?? / 30                                          73 / -> PRG RAM A16
                     /                                            72 / -> PRG RAM 1 /CE (R)
                     /                                            72 / -> PRG RAM 1 /CE (R)
                     \                                            71 / -> PRG RAM 0 /CE (R)
                     \                                            71 / -> PRG RAM 0 /CE (R)

Revision as of 11:18, 13 November 2018

                                                   _____
                                                  /     \
                        Audio Amplifier Input -> / 1 100 \ -> Audio Amplifier Output
                                   Audio DAC <- / 2    99 \ -- AGnd
                          Audio Pulse Waves <- / 3  (*) 98 \ ?? SL3 (unknown input) *
                                  +5V AVcc -- / 4        97 \ ?? CL3 (unknown input) *
                              (fr) PPU A0 -> / 5          96 \ -> CHR A2 *
                             (fr) PPU A1 -> / 6            95 \ -> CHR A1 *
                            (fr) PPU A2 -> / 7              94 \ -> CHR A0 *
                           (fr) PPU A3 -> / 8                93 \ -> PRG RAM A15
                          (fr) PPU A4 -> / 9                  92 \ ?? (unknown input)
                         (fr) PPU A5 -> / 10                   91 \ <> PPU D7 (fr)
                        (fr) PPU A6 -> / 11                     90 \ <> PPU D6 (fr)
                       (fr) PPU A7 -> / 12                       89 \ <> PPU D5 (fr)
                      (fr) PPU A8 -> / 13                         88 \ <> PPU D4 (fr)
                     (fr) PPU A9 -> / 14                           87 \ <> PPU D3 (fr)
                    (r) CHR A10 <- / 15                             86 \ <> PPU D2 (fr)
                   (r) CHR A11 <- / 16                               85 \ <> PPU D1 (fr)
                  (r) CHR A12 <- / 17                                 84 \ <> PPU D0 (fr)
                 (r) CHR A13 <- / 18                                   83 \ -> PRG RAM +CE
                (r) CHR A14 <- / 19                                     82 \ ?? (unknown input)
               (r) CHR A15 <- / 20                                       81 \ ?? (unknown input)
              (r) CHR A16 <- / 21                                            \
             (r) CHR A17 <- / 22                                             /
            (r) CHR A18 <- / 23                                          80 / -- DGnd
           (r) CHR A19 <- / 24                                          79 / <- M2 (f)
          (f) PPU A10 -> / 25                                          78 / <- /ROMSEL (f)
         (f) PPU A11 -> / 26              Nintendo MMC5               77 / <- CPU R/W (f)
        (f) PPU A12 -> / 27      Package QFP-100, 0.65mm pitch       76 / -> PRG RAM /WE (R)
      (f) PPU /A13 -> / 28                                          75 / -> PRG RAM /CE (RAM0/CE & RAM1/CE)
  (unknown input) ?? / 29                                          74 / -> PRG /CE (r)
 (unknown input) ?? / 30                                          73 / -> PRG RAM A16
                   /                                             72 / -> PRG RAM 1 /CE (R)
                   \                                            71 / -> PRG RAM 0 /CE (R)
   (f) CIRAM /CE <- \ 31                                       70 / -> PRG RAM A14 (R)
    (f) CIRAM A10 <- \ 32                                     69 / -> PRG RAM A13 (R)
       (f) PPU /WR -> \ 33                                   68 / <- CPU A14 (f)
        (f) PPU /RD -> \ 34                                 67 / <- CPU A13 (f)
            (f) /IRQ <- \ 35                               66 / -> PRG A19 (r)
          (fr) CPU D0 <> \ 36                             65 / -> PRG A18 (r)
           (fr) CPU D1 <> \ 37                           64 / -> PRG A17 (r)
            (fr) CPU D2 <> \ 38                         63 / -> PRG A16 (r)
             (fr) CPU D3 <> \ 39                       62 / -> PRG A15 (r)
              (fr) CPU D4 <> \ 40                     61 / -> PRG A14 (r)
               (fr) CPU D5 <> \ 41                   60 / -> PRG A13 (r)
                (fr) CPU D6 <> \ 42                 59 / <- CPU A12 (fr)
                 (fr) CPU D7 <> \ 43               58 / <- CPU A11 (fr)
                     +5V DVcc -- \ 44             57 / -- + Backup battery
                   (fr) CPU A0 -> \ 45           56 / -> PRG RAM Vcc Output   Legend:
                    (fr) CPU A1 -> \ 46         55 / <- CPU A10 (fr)          ------------------------------
                     (fr) CPU A2 -> \ 47       54 / <- CPU A9 (fr)            --[MMC5]-- Power
                      (fr) CPU A3 -> \ 48  O  53 / <- CPU A8 (fr)             ->[MMC5]<- MMC5 input
                       (fr) CPU A4 -> \ 49   52 / <- CPU A7 (fr)              <-[MMC5]-> MMC5 output
                        (fr) CPU A5 -> \ 50 51 / <- CPU A6 (fr)               <>[MMC5]<> Bidirectional
                                        \     /                               ??[MMC5]?? Unknown
                                         \   /                                    f      Famicom connection
                                          \ /                                     r      ROM chip connection
                                           V                                      R      RAM chip connection

Orientation: 

    80         51
     |         |
    .-----------.
 81-| Nintendo o|-50
    | MMC5      |
100-|@          |-31
    \-----------'
     |         |
    01         30
Pin Function Pin Function Pin Function Pin Function
1 Amplifier Input 51 CPU A6
2 DAC 52 CPU A7
3 Pulse Waves 53 CPU A8
4 VCC 54 CPU A9
5 PPU A0 55 CPU A10
6 PPU A1 31 CIRAM /CE 56 PRG RAM VCC 81 (unk. output)
7 PPU A2 32 CIRAM A10 57 +batt 82 (unk. output)
8 PPU A3 33 PPU /WR 58 CPU A11 83 PRG RAM +CE
9 PPU A4 34 PPU /RD 59 CPU A12 84 PPU D0
10 PPU A5 35 /IRQ 60 PRG A13 85 PPU D1
11 PPU A6 36 CPU D0 61 PRG A14 86 PPU D2
12 PPU A7 37 CPU D1 62 PRG A15 87 PPU D3
13 PPU A8 38 CPU D2 63 PRG A16 88 PPU D4
14 PPU A9 39 CPU D3 64 PRG A17 89 PPU D5
15 CHR A10 40 CPU D4 65 PRG A18 90 PPU D6
16 CHR A11 41 CPU D5 66 PRG A19 91 PPU D7
17 CHR A12 42 CPU D6 67 CPU A13 92 (unk. output)
18 CHR A13 43 CPU D7 68 CPU A14 93 (unk. output)
19 CHR A14 44 VCC 69 PRG RAM A13 94 CHR A0 †
20 CHR A15 45 CPU A0 70 PRG RAM A14 95 CHR A1 †
21 CHR A16 46 CPU A1 71 PRG RAM 0 /CE 96 CHR A2 †
22 CHR A17 47 CPU A2 72 PRG RAM 1 /CE 97 CL3 †
23 CHR A18 48 CPU A3 73 (unk. output) 98 SL3 †
24 CHR A19 49 CPU A4 74 PRG /CE 99 GND
25 PPU A10 50 CPU A5 75 (RAM control?) 100 Amplifier output
26 PPU A11 76 PRG RAM /WE
27 PPU A12 77 CPU R/W
28 PPU /A13 78 /ROMSEL
29 (unk. output) 79 M2
30 (unk. output) 80 GND

†PINS 94 thru 98: These set the cart to either CL or SL mode.

To set to CL mode:

  • Connect PPU A0 from the NES to A0 on the CHR ROM.
  • Connect PPU A1 from the NES to A1 on the CHR ROM.
  • Connect PPU A2 from the NES to A2 on the CHR ROM.
  • Connect pins 97 and 98 together.
  • Leave pins 94,95 & 96 floating on the MMC5

To set to SL mode:

  • Connect pin 94 of the MMC5 to A0 of the CHR ROM.
  • Connect pin 95 of the MMC5 to A1 of the CHR ROM.
  • Connect pin 96 of the MMC5 to A2 of the CHR ROM.
  • Connect pin 98 to ground.
  • Leave pin 97 floating.

In other words, CL mode passes the lowest PPU address bits straight to CHR ROM, while SL mode runs them through MMC5. SL mode allows the MMC5 to perform smooth vertical scrolling in split mode, while CL mode does not. Nearly all MMC5 cartridges use CL mode - it is not known why SL mode was not used instead: possibly ROM speed issues.

Audio circuit topology for HVC-ExROM boards:

MMC5 audio.png

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