MMC6 pinout: Difference between revisions

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(Added C8 to BOM. Verified the number '8' carefully with microscope.)
 
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<pre>
                                        ___
    48   33
                                        /  \
    |   |
                                      /    \
  .------.
                      (n) CPU A13 -> / 1  64 \ -> PRG A17 (r)
49-|     |-32
                              M2 -> / 2    63 \ <- CPU A14 (n)
   | MMC6 |
                  (unknown, GND) -> / 3  O  62 \ -> PRG A18 (r)
64-|     |-17
                            n/c -- / 4        61 \ -> PRG A14 (r)
  \------'
                          n/c -- / 5          60 \ -> PRG A15 (r)
    |   |
                          /M2 <- / 6            59 \ -> PRG A13 (r)
     01   16
              (unknown, GND) -> / 7              58 \ <- CPU A12 (nr)
</pre>
              (unknown, 5V) -> / 8                57 \ -- GND
            (unknown, 5V) -> / 9                  56 \ -- VCC/batt
                VCC/batt -- / 10                  55 \ <- CPU A8 (nr)
                    GND -- / 11              ( )    54 \ <- CPU A7 (nr)
          (unknown, 5V) -> / 12                      53 \ <- CPU A9 (nr)
        3.3V Core Bias -- / 13                        52 \ <- CPU A6 (nr)
          (n) PPU A10 -> / 14                          51 \ <- CPU A5 (nr)
        (n) PPU A11 -> / 15                            50 \ -> PRG A16 (r)
PPU /RD || PPU A13 <- / 16                              49 \ <- CPU A4 (nr)    Orientation:
                      /            Nintendo MMC6            \                  --------------------
                      \      Package QFP-64, 0.8mm pitch      /                    48         33
        (r) CHR A10 <- \ 17                              48 / <- CPU A3 (nr)        |         |
        (r) CHR A16 <- \ 18                            47 / -> PRG /CE (r)        .------------.
          (r) CHR A11 <- \ 19                          46 / <- CPU A2 (nr)      49-|           |-32
          (n) PPU A12 -> \ 20                        45 / <> CPU D7 (nr)          |  Nintendo  |
            (r) CHR A13 <- \ 21   ( )                44 / <- CPU A1 (nr)          |O  MMC6B  O|
            (r) CHR A12 <- \ 22                    43 / <> CPU D6 (nr)            |           |
              (r) CHR A14 <- \ 23                  42 / <- CPU A0 (nr)          64-|o          |-17
                      GND -- \ 24                41 / <> CPU D5 (nr)              \------------'
                  VCC/batt -- \ 25              40 / <> CPU D0 (nr)                |         |
                (r) CHR A15 <- \ 26            39 / <> CPU D4 (nr)                1          16
                (n) CIRAM A10 <- \ 27          38 / -- VCC/batt
        (nr) CHR /OE, PPU /RD -> \ 28        37 / -- GND            Legend:
          (nr) CHR /CE, PPU A13 -> \ 29      36 / <> CPU D1 (nr)      ------------------------------
                    (r) CHR A17 <- \ 30     35 / <> CPU D3 (nr)      --[MMC6]-- Power
                        (n) /IRQ <- \ 31   34 / <> CPU D2 (nr)        ->[MMC6]<- MMC6 input
                      (n) /ROMSEL -> \ 32 33 / <- CPU R/W (n)        <-[MMC6]-> MMC6 output
                                      \    /                        <>[MMC6]<> Bidirectional
                                        \  /                          ??[MMC6]?? Unknown
                                        \ /                              n      NES connection
                                          V                                r      ROM chip connection


{| border=1
* GND pins (11,24,37,57) are internally connected to each other.
! Pin || Function || Pin || Function || Pin || Function || Pin || Function
* VCC/batt pins (10,25,38,56) are internally connected to each other.
|-
* All pins have internal protection diodes from GND and to VCC/batt except pins 4 and 5.
| 01 || CPU A13 || 17 || CHR A10 || 33 || R/W || 49 || CPU A4
* Pins 4 and 5 measure infinite resistance to all other pins.
|-
* Unknown input pins (3,7,8,9,12) are labeled per connections on NES-HKROM PCB.
| 02 || M2 || 18 || CHR A16 || 34 || CPU D2 || 50 || PRG A16
|-
| 03 || GND || 19 || CHR A11 || 35 || CPU D3 || 51 || CPU A5
|-
| 04 || GND || 20 || PPU A12 || 36 || CPU D1 || 52 || CPU A6
|-
| 05 || GND || 21 || CHR A13 || 37 || GND || 53 || CPU A9
|-
| 06 || NC || 22 || CHR A12 || 38 || +batt || 54 || CPU A7
|-
| 07 || GND || 23 || CHR A14 || 39 || CPU D4 || 55 || CPU A8
|-
| 08 || VCC || 24 || GND || 40 || CPU D0 || 56 || +batt
|-
| 09 || VCC || 25 || +batt || 41 || CPU D5 || 57 || GND
|-
| 10 || +batt || 26 || CHR /CE? || 42 || CPU A0 || 58 || CPU A12
|-
| 11 || GND || 27 || VRAM A10 || 43 || CPU D6 || 59 || PRG A13
|-
| 12 || VCC || 28 || PPU /RD || 44 || CPU A1 || 60 || PRG A15
|-
| 13 || threshold* || 29 || PPU A13 || 45 || CPU D7 || 61 || PRG A14
|-
| 14 || PPU A10 || 30 || CHR A17 || 46 || CPU A2 || 62 || PRG A18
|-
| 15 || PPU A11 || 31 || /IRQ || 47 || PRG /CE || 63 || CPU A14
|-
| 16 || NC || 32 || CPU /CE || 48 || CPU A3 || 64 || PRG A17
|}


*Threshold: tied to a resistor divider between +5V and GND; resistor to +5V is 180 ohms, resistor to ground is 470 ohms.
 
Battery Circuit from NES-HKROM PCB:
 
    +------|>|----/\/\/------+------|<|-----O  NES 5V
+  |            1 kohm    |
  ---  3V                  |
  ----- Lithium              +--------------O  MMC6 VCC/Batt
    |  2032
-  |
    +---------------------------------------O  NES GND, MMC6 GND
 
 
3.3V Core Bias Circuit from NES-HKROM PCB:
 
            NES 5V  O----/\/\/----+
                        181 ohm  |
                                  |
                                  +-----O  MMC6 3.3V Core Bias
                                  |
                        470 ohm  |
NES GND, MMC6 GND  O----/\/\/----+
 
 
NES-HKROM (Startropics 1) BOM:
R1  1 kohm
R2  181 ohm
R3  470 ohm
C1  22uF 6.3V Electrolytic
C2  10nF Ceramic
C3  10nF Ceramic
C8  22uF 6.3V Electrolytic
D1  Diode (0.6V Forward)
D2  Diode (0.6V Forward)
U1  PRG-ROM
U2  CHR-ROM
U3  CIC
U4  MMC6
Batt 2032 3V Lithium


[[Category:Pinouts]]
[[Category:Pinouts]]

Latest revision as of 18:08, 19 January 2019

                                        ___
                                       /   \
                                      /     \
                      (n) CPU A13 -> / 1  64 \ -> PRG A17 (r)
                              M2 -> / 2    63 \ <- CPU A14 (n)
                 (unknown, GND) -> / 3   O  62 \ -> PRG A18 (r)
                           n/c -- / 4        61 \ -> PRG A14 (r)
                          n/c -- / 5          60 \ -> PRG A15 (r)
                         /M2 <- / 6            59 \ -> PRG A13 (r)
             (unknown, GND) -> / 7              58 \ <- CPU A12 (nr)
             (unknown, 5V) -> / 8                57 \ -- GND
            (unknown, 5V) -> / 9                  56 \ -- VCC/batt
                VCC/batt -- / 10                   55 \ <- CPU A8 (nr)
                    GND -- / 11              ( )    54 \ <- CPU A7 (nr)
         (unknown, 5V) -> / 12                       53 \ <- CPU A9 (nr)
       3.3V Core Bias -- / 13                         52 \ <- CPU A6 (nr)
         (n) PPU A10 -> / 14                           51 \ <- CPU A5 (nr)
        (n) PPU A11 -> / 15                             50 \ -> PRG A16 (r)
PPU /RD || PPU A13 <- / 16                               49 \ <- CPU A4 (nr)    Orientation:
                     /             Nintendo MMC6             \                  --------------------
                     \      Package QFP-64, 0.8mm pitch      /                     48          33
       (r) CHR A10 <- \ 17                               48 / <- CPU A3 (nr)        |          |
        (r) CHR A16 <- \ 18                             47 / -> PRG /CE (r)        .------------.
         (r) CHR A11 <- \ 19                           46 / <- CPU A2 (nr)      49-|            |-32
          (n) PPU A12 -> \ 20                         45 / <> CPU D7 (nr)          |  Nintendo  |
           (r) CHR A13 <- \ 21    ( )                44 / <- CPU A1 (nr)           |O  MMC6B   O|
            (r) CHR A12 <- \ 22                     43 / <> CPU D6 (nr)            |            |
             (r) CHR A14 <- \ 23                   42 / <- CPU A0 (nr)          64-|o           |-17
                      GND -- \ 24                 41 / <> CPU D5 (nr)              \------------'
                  VCC/batt -- \ 25               40 / <> CPU D0 (nr)                |          |
                (r) CHR A15 <- \ 26             39 / <> CPU D4 (nr)                 1          16
               (n) CIRAM A10 <- \ 27           38 / -- VCC/batt
        (nr) CHR /OE, PPU /RD -> \ 28         37 / -- GND             Legend:
         (nr) CHR /CE, PPU A13 -> \ 29       36 / <> CPU D1 (nr)      ------------------------------
                    (r) CHR A17 <- \ 30     35 / <> CPU D3 (nr)       --[MMC6]-- Power
                        (n) /IRQ <- \ 31   34 / <> CPU D2 (nr)        ->[MMC6]<- MMC6 input
                      (n) /ROMSEL -> \ 32 33 / <- CPU R/W (n)         <-[MMC6]-> MMC6 output
                                      \     /                         <>[MMC6]<> Bidirectional
                                       \   /                          ??[MMC6]?? Unknown
                                        \ /                               n      NES connection
                                         V                                r      ROM chip connection
  • GND pins (11,24,37,57) are internally connected to each other.
  • VCC/batt pins (10,25,38,56) are internally connected to each other.
  • All pins have internal protection diodes from GND and to VCC/batt except pins 4 and 5.
  • Pins 4 and 5 measure infinite resistance to all other pins.
  • Unknown input pins (3,7,8,9,12) are labeled per connections on NES-HKROM PCB.


Battery Circuit from NES-HKROM PCB:

   +------|>|----/\/\/------+------|<|-----O  NES 5V
+  |             1 kohm     |
  ---  3V                   |
 ----- Lithium              +--------------O  MMC6 VCC/Batt
   |   2032
-  |
   +---------------------------------------O  NES GND, MMC6 GND


3.3V Core Bias Circuit from NES-HKROM PCB:

           NES 5V  O----/\/\/----+
                       181 ohm   |
                                 |
                                 +-----O  MMC6 3.3V Core Bias
                                 |
                       470 ohm   |
NES GND, MMC6 GND  O----/\/\/----+


NES-HKROM (Startropics 1) BOM:

R1  1 kohm
R2  181 ohm
R3  470 ohm
C1  22uF 6.3V Electrolytic
C2  10nF Ceramic
C3  10nF Ceramic
C8  22uF 6.3V Electrolytic
D1  Diode (0.6V Forward)
D2  Diode (0.6V Forward)
U1  PRG-ROM
U2  CHR-ROM
U3  CIC
U4  MMC6
Batt 2032 3V Lithium