Mask ROM pinout: Difference between revisions
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m (→128/256/512 KBytes (28/32pin) ROMs: USA NES games with Konami boards apparently uses Nintendo's pinout (looking at the # of pins on bootgod's database).) |
(combined everything into one narrow diagram as Blarg wishes, added info/speculaiton about unused pins) |
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For some unknown reasons, unused address lines on smaller ROMs '''had to be''' put to +5V, as Nintendo made different boards for each size (as opposed to place EPROMs of different sizes into the same slot). Some boards, such as CNROM, features solder pads in order to force those pins to +5V though. | For some unknown reasons, unused address lines on smaller ROMs '''had to be''' put to +5V, as Nintendo made different boards for each size (as opposed to place EPROMs of different sizes into the same slot). Some boards, such as CNROM, features solder pads in order to force those pins to +5V though. | ||
As Nintendo liked to use Mask ROMs from various manufacturers, apparently unused pins could be either not connected or additional active high CE enable lines. This would ensure that if Nintendo would order mask ROMs with additional enable lines that aren't used, they could place them on the board without having the fear of having them disabled accidentally. | |||
This doesn't apply to CHR ROMs - i.e. a smaller ROM can always fit a slot made with a larger ROM in mind. | This doesn't apply to CHR ROMs - i.e. a smaller ROM can always fit a slot made with a larger ROM in mind. Probably as the game will work if the ROM is "accidentally" disabled before the first write to CHR bankswitching registers. | ||
<pre style="display:inline-block"> | <pre style="display:inline-block"> | ||
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== 128/256/512 KBytes (28/32pin) ROMs == | == 128/256/512 KBytes (28/32pin) ROMs == | ||
Nintendo used the | Nintendo used the standard pinout for (extremely rare) prototype boards intended to take a 27C010/020/040 EPROMs. | ||
But retail Game Paks made by Nintendo have mask ROMs with a different pinout which is not JEDEC compatible. | But retail Game Paks made by Nintendo have mask ROMs with a different pinout which is not JEDEC compatible. | ||
This pinout, with reshuffled enable lines and higher address lines | This pinout, with reshuffled enable lines and higher address lines, allows a 32-pin hole to take a 28-pin 128 KB PRG ROM in pin 3 to pin 30. | ||
Other licenced or unlicenced companies producing Famicom or NES boards with ROMs of those sizes, used either epoxy blobs or standard EPROM pinout. The only known exception to this is Konami boards for NES games however, uses Nintendo's 'PRG' pinout (for both the PRG and CHR), using an additional 74HC32 to combine CHR /RD and CHR /A13 into a single /CE signal like SL1ROM and TL1ROM. This doesn't apply to Famicom Konami boards, which uses standard pinout. | |||
On Nintendo's boards where PRG A18 is never used, pin 2 is connected with pin 22. | |||
Nintendo's MMC5 boards which supports up to 1MB of data. Both PRG and CHR ROMs are the same pinout, and even 128 KB PRG ROMs are 32-pin so they can have a VCC pin. | |||
<pre style="display:inline-block"> | <pre style="display:inline-block"> | ||
CHR ROM, PRG ROM, and 27C010/020/040/080 EPROM pinouts compared | |||
MMC5 CHR PRG EPROM EPROM PRG CHR MMC5 | |||
---_--- | |||
A17 A17 [+5V] A17 [VPP] A19 - |01 32| - +5V | |||
A18 /CE A18 [/CE] A16 - |02 31| - A18 [PGM] +5V /CE /CE | |||
A15 - |03 30| - A17 [NC] +5V +5V A19 | |||
A12 - |04 29| - A14 | |||
PRG | A7 - |05 28| - A13 | ||
PRG | A6 - |06 27| - A8 | ||
A5 - |07 26| - A9 | |||
A4 - |08 25| - A11 | |||
A3 - |09 24| - /OE A16 A16 A16 | |||
A2 - |10 23| - A10 | |||
A1 - |11 22| - /CE | |||
A0 - |12 21| - D7 | |||
D0 - |13 20| - D6 | |||
D1 - |14 19| - D5 | |||
D2 - |15 18| - D4 | |||
GND - |16 17| - D3 | |||
------- | |||
PRG and CHR pins are listed only if they differ from EPROM. On PRG, all address lines are from PRG bus. On CHR, all address lines are from CHR bus, unless noted. | |||
</pre> | </pre> | ||
== Variants == | == Variants == | ||
Here is a list of multiple variants of Nintendo's pinouts above. Only a couple of enable pins typically differs (which are shown in bold). | Here is a list of multiple variants of Nintendo's pinouts above. Only a couple of enable pins typically differs (which are shown in bold). | ||
=== Nintendo AOROM PRG ROM pinout - 128/256/KBytes (32pin) === | === Nintendo AOROM PRG ROM pinout - 128/256/KBytes (32pin) === | ||
Revision as of 10:37, 8 December 2010
8kB / 16kB / 32kB / 64kBytes (28pin) ROMs
Nintendo used by default JEDEC standard compatible pinout for all their mask ROMs of 64 kByes and below. Names [in brackets] applies when the corresponding address pin is unused. On boards where an adress pin is never used (for example, A15 is never used on NROM boards as the ROM can't be greater than 32k), what is in brackets connects to the unused pin.
For some unknown reasons, unused address lines on smaller ROMs had to be put to +5V, as Nintendo made different boards for each size (as opposed to place EPROMs of different sizes into the same slot). Some boards, such as CNROM, features solder pads in order to force those pins to +5V though. As Nintendo liked to use Mask ROMs from various manufacturers, apparently unused pins could be either not connected or additional active high CE enable lines. This would ensure that if Nintendo would order mask ROMs with additional enable lines that aren't used, they could place them on the board without having the fear of having them disabled accidentally.
This doesn't apply to CHR ROMs - i.e. a smaller ROM can always fit a slot made with a larger ROM in mind. Probably as the game will work if the ROM is "accidentally" disabled before the first write to CHR bankswitching registers.
27C64/128/256/512 EPROM pinout
---_---
[+5V] A15 - |01 28| - +5V
A12 - |02 27| - A14 [PGM]
A7 - |03 26| - A13 [NC]
A6 - |04 25| - A8
A5 - |05 24| - A9
A4 - |06 23| - A11
A3 - |07 22| - /OE
A2 - |08 21| - A10
A1 - |09 20| - /CE
A0 - |10 19| - D7
D0 - |11 18| - D6
D1 - |12 17| - D5
D2 - |13 16| - D4
GND - |14 15| - D3
-------
128/256/512 KBytes (28/32pin) ROMs
Nintendo used the standard pinout for (extremely rare) prototype boards intended to take a 27C010/020/040 EPROMs. But retail Game Paks made by Nintendo have mask ROMs with a different pinout which is not JEDEC compatible. This pinout, with reshuffled enable lines and higher address lines, allows a 32-pin hole to take a 28-pin 128 KB PRG ROM in pin 3 to pin 30.
Other licenced or unlicenced companies producing Famicom or NES boards with ROMs of those sizes, used either epoxy blobs or standard EPROM pinout. The only known exception to this is Konami boards for NES games however, uses Nintendo's 'PRG' pinout (for both the PRG and CHR), using an additional 74HC32 to combine CHR /RD and CHR /A13 into a single /CE signal like SL1ROM and TL1ROM. This doesn't apply to Famicom Konami boards, which uses standard pinout.
On Nintendo's boards where PRG A18 is never used, pin 2 is connected with pin 22.
Nintendo's MMC5 boards which supports up to 1MB of data. Both PRG and CHR ROMs are the same pinout, and even 128 KB PRG ROMs are 32-pin so they can have a VCC pin.
CHR ROM, PRG ROM, and 27C010/020/040/080 EPROM pinouts compared
MMC5 CHR PRG EPROM EPROM PRG CHR MMC5
---_---
A17 A17 [+5V] A17 [VPP] A19 - |01 32| - +5V
A18 /CE A18 [/CE] A16 - |02 31| - A18 [PGM] +5V /CE /CE
A15 - |03 30| - A17 [NC] +5V +5V A19
A12 - |04 29| - A14
A7 - |05 28| - A13
A6 - |06 27| - A8
A5 - |07 26| - A9
A4 - |08 25| - A11
A3 - |09 24| - /OE A16 A16 A16
A2 - |10 23| - A10
A1 - |11 22| - /CE
A0 - |12 21| - D7
D0 - |13 20| - D6
D1 - |14 19| - D5
D2 - |15 18| - D4
GND - |16 17| - D3
-------
PRG and CHR pins are listed only if they differ from EPROM. On PRG, all address lines are from PRG bus. On CHR, all address lines are from CHR bus, unless noted.
Variants
Here is a list of multiple variants of Nintendo's pinouts above. Only a couple of enable pins typically differs (which are shown in bold).
Nintendo AOROM PRG ROM pinout - 128/256/KBytes (32pin)
Very slight variant of the standard PRG-ROM pinout above, where an additional active high enable line is used to prevent bus conflicts.
---_---
PRG A17 - |01 32| - +5V
PRG /CE - |02 31| - CE (R/W)
PRG A15 - |03 30| - +5V
PRG A12 - |04 29| - PRG A14
PRG A7 - |05 28| - PRG A13
PRG A6 - |06 27| - PRG A8
PRG A5 - |07 26| - PRG A9
PRG A4 - |08 25| - PRG A11
PRG A3 - |09 24| - PRG A16
PRG A2 - |10 23| - PRG A10
PRG A1 - |11 22| - PRG /CE
PRG A0 - |12 21| - PRG D7
PRG D0 - |13 20| - PRG D6
PRG D1 - |14 19| - PRG D5
PRG D2 - |15 18| - PRG D4
GND - |16 17| - PRG D3
-------
Signal descriptions
- A0-A12
- address
- D0-D7
- data
- /CE, /OE
- The ROM will output data at adress A on pins D only if all it's CE and OE pins are active (CE active high, /CE active low).
- PGM, VPP
- Used only during EPROM programing / erasing process.
See here for other signals descriptions.
