NES 2.0 Mapper 266: Difference between revisions

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{{DEFAULTSORT:266}}[[Category:Mappers with cycle IRQs]]NES 2.0 Mapper 266 is used by ''City Fighter IV'', a hack of ''Master Fighter II'' that adds (very grungy) PCM speech output. Given that its resolution (four bits) is worse than the NES/Famicom's own DAC at $4011 (seven bits), it's not immediately obvious what the purpose of including its own DAC is, other than perhaps the possibility of low-pass filtering the 3.5 kHz-sampled PCM data on the circuit board. Its UNIF board name is '''UNL-CITYFIGHT'''.
{{DEFAULTSORT:266}}[[Category:Mappers with cycle IRQs]]'''NES 2.0 Mapper 266''' is used by ''City Fighter IV'', a hack of ''Master Fighter II'' that adds (very grungy) PCM speech output. Given that its resolution (four bits) is worse than the NES/Famicom's own DAC at $4011 (seven bits), it's not immediately obvious what the purpose of including its own DAC is, other than perhaps the possibility of low-pass filtering the 3.5 kHz-sampled PCM data on the circuit board. Its UNIF board name is '''UNL-CITYFIGHT'''.
=Registers=
==Mirroring ($9000)==
Mask: Probably $F808
7654 3210
---------
.... ..MM
        ++- Set nametable mirroring
            0: Vertical
            1: Horizontal
            2: One-screen page 0
            3: One-screen page 1
   
==PRG-ROM Bank ($9008)==
Mask: Probably $F808
7654 3210
---------
.... PP..
      ++--- Select 32 KiB PRG-ROM bank at CPU $8000-$FFFF


==PRG Banking Mode ($C000)==
The circuit board mounts a [[VRC4]] clone (A2/A3) with two of its higher CPU address lines mixed up:
Mask: Probably $F000
  CPU A3  -> VRC4 CPU Ax (pin 03)
  7654 3210
CPU A2 -> VRC4 CPU Ay (pin 04)
  ---------
CPU A13 -> VRC4 CPU A14 (pin 02)
.... ...M
CPU A14 -> VRC4 CPU A13 (pin 01)
        +- Set PRG Mode
... and two additional registers that are selected via the VRC4 /WR9003 pin, e.g. by writing to $900C, and distinguished via CPU A11 ($0800). This results in the following effective registers:
            0: $C000-$DFFF is a mirror of $8000-$9FFF
            1: $C000-$DFFF is not a mirror of $8000-$9FFF


==PCM Output ($9800)==
==Mirroring Control ($9000)==
Mask: Probably $F800
Mask: $F00C, see [[VRC2_and_VRC4#Mirroring_Control_.28.249000.2C_.249001.2C_.249002.2C_.249003.29|VRC4 description]].
7654 3210
---------
.... PPPP
      ++++- Unsigned PCM data


==CHR-ROM Banks ($A000-$BFFF, $D000-$EFFF)==
==PRG Select ($900C)==
Mask: Probably $F00C
Mask: $F80C
D~7654 3210
  ---------
  .... PP..
        ++--- CPU A16..A15
 
Similar to [[INES Mapper 189]], VRC4's fine-grained PRG banking is replaced with a single 32 KiB bank switch.


A000    Set 1 KiB CHR-ROM bank at PPU $0800-$0BFF (low nibble)
==DAC Output ($980C)==
A004    Set 1 KiB CHR-ROM bank at PPU $0800-$0BFF (high nibble)
  Mask: $F80C
  A008    Set 1 KiB CHR-ROM bank at PPU $0C00-$0FFF (low nibble)
A00C    Set 1 KiB CHR-ROM bank at PPU $0C00-$0FFF (high nibble)
B000    Set 1 KiB CHR-ROM bank at PPU $1000-$13FF (low nibble)
B004    Set 1 KiB CHR-ROM bank at PPU $1000-$13FF (high nibble)
B008    Set 1 KiB CHR-ROM bank at PPU $1400-$17FF (low nibble)
B00C    Set 1 KiB CHR-ROM bank at PPU $1400-$17FF (high nibble)
D000    Set 1 KiB CHR-ROM bank at PPU $0000-$03FF (low nibble)
D004    Set 1 KiB CHR-ROM bank at PPU $0000-$03FF (high nibble)
D008    Set 1 KiB CHR-ROM bank at PPU $0400-$07FF (low nibble)
D00C    Set 1 KiB CHR-ROM bank at PPU $0400-$07FF (high nibble)
E000    Set 1 KiB CHR-ROM bank at PPU $1800-$1BFF (low nibble)
E004    Set 1 KiB CHR-ROM bank at PPU $1800-$1BFF (high nibble)
E008    Set 1 KiB CHR-ROM bank at PPU $1C00-$1FFF (low nibble)
E00C    Set 1 KiB CHR-ROM bank at PPU $1C00-$1FFF (high nibble)
   
   
  7654 3210
  D~7654 3210
---------
  ---------
.... PPPP
  .... DDDD
      ++++- 1 KiB CHR bank number (low/high nibble depending on address)
        ++++- 4 bit unsigned PCM data


==IRQ Counter ($F000/$F004)==
==CHR Select ($A00x/$B00x/$D00x/$C00x)==
Mask: Probably $F00C
Mask: $F80C
F000    Set low nibble of 8-bit IRQ counter
F004    Set high nibble of 8-bit IRQ counter
   
   
  7654 3210
  $D000/$D004 (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $0000-$03FF
  ---------
  $D008/$D00C (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $0400-$07FF
  .... VVVV
$A000/$A004 (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $0800-$0BFF
      ++++- IRQ counter data (low/high nibble depending on address)
$A008/$A00C (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $0C00-$0FFF
   
$B000/$B004 (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $1000-$13FF
==IRQ Enable/Acknowledge($F008)==
$B008/$B00C (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $1400-$17FF
Mask: Probably $F008
  $E000/$E004 (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $1800-$1BFF
7654 3210
  $E008/$E00C (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $1C00-$1FFF
---------
==IRQ Control ($F00x)==
.... ..E.
Mask: $F00C, see [[VRC2_and_VRC4#IRQ_Control_.28.24F00x.29_VRC4|VRC4 description]].
        +-- 1=Enable IRQ
 
Writing to this register also acknowledges the IRQ.
=Notes=
             
The game uses the VRC4's pseudo-scanline mode during speech output. FCEUX only emulates a downward-counting CPU cycle counter, counting on every other cycle, causing speech to be played at too low a pitch compared to hardware.
=IRQ operation=
If the IRQ is enabled, the counter is decremented on every ''second'' M2 cycle. If it becomes zero, an IRQ is raised.

Revision as of 19:33, 14 March 2020

NES 2.0 Mapper 266 is used by City Fighter IV, a hack of Master Fighter II that adds (very grungy) PCM speech output. Given that its resolution (four bits) is worse than the NES/Famicom's own DAC at $4011 (seven bits), it's not immediately obvious what the purpose of including its own DAC is, other than perhaps the possibility of low-pass filtering the 3.5 kHz-sampled PCM data on the circuit board. Its UNIF board name is UNL-CITYFIGHT.

The circuit board mounts a VRC4 clone (A2/A3) with two of its higher CPU address lines mixed up:

CPU A3  -> VRC4 CPU Ax (pin 03)
CPU A2  -> VRC4 CPU Ay (pin 04)
CPU A13 -> VRC4 CPU A14 (pin 02)
CPU A14 -> VRC4 CPU A13 (pin 01)

... and two additional registers that are selected via the VRC4 /WR9003 pin, e.g. by writing to $900C, and distinguished via CPU A11 ($0800). This results in the following effective registers:

Mirroring Control ($9000)

Mask: $F00C, see VRC4 description.

PRG Select ($900C)

Mask: $F80C

D~7654 3210
  ---------
  .... PP..
       ++--- CPU A16..A15

Similar to INES Mapper 189, VRC4's fine-grained PRG banking is replaced with a single 32 KiB bank switch.

DAC Output ($980C)

Mask: $F80C

D~7654 3210
  ---------
  .... DDDD
       ++++- 4 bit unsigned PCM data

CHR Select ($A00x/$B00x/$D00x/$C00x)

Mask: $F80C

$D000/$D004 (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $0000-$03FF
$D008/$D00C (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $0400-$07FF
$A000/$A004 (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $0800-$0BFF
$A008/$A00C (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $0C00-$0FFF
$B000/$B004 (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $1000-$13FF
$B008/$B00C (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $1400-$17FF
$E000/$E004 (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $1800-$1BFF
$E008/$E00C (LSB/MSB): Select 1 KiB CHR-ROM bank at PPU $1C00-$1FFF

IRQ Control ($F00x)

Mask: $F00C, see VRC4 description.

Notes

The game uses the VRC4's pseudo-scanline mode during speech output. FCEUX only emulates a downward-counting CPU cycle counter, counting on every other cycle, causing speech to be played at too low a pitch compared to hardware.