NES 2.0 Mapper 296: Difference between revisions

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(Category)
(New register bits used by NX-85 TV Game Console)
 
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             1: CHR-RAM (unbanked)
             1: CHR-RAM (unbanked)


==CPU Encryption Control ($411E, write)==
==Encryption Control ($411E, write)==
The multicart menu writes $00 to disable and $05 to enable encryption ''after the next JMP instruction''. When encryption is active, CPU opcode bytes only are XORed with $A1.
7654 3210
---------
cc.. .C.C
||    +-+- 00: Disable CPU opcode encryption after the next JMP instruction
||        11: Enable CPU opcode encryption after the next JMP instruction
++-------- 00: Disable CHR data encryption
            11: Enable CHR data encryption
 
* When CPU encryption is active, CPU opcode bytes only are XORed with $A1.
* When CHR data encryption is active, CHR data bytes' bits 0 and 4, 1 and 2, 3 and 7, and 5 and 6 are swapped.


==Outer Bank Register ($412C)==
==Outer Bank Register ($412C)==
  7654 3210
  7654 3210
  ---------
  ---------
  .... ..CP
  .... cpCP
        |+- PRG A25 (32 MiB)
      |||+- PRG A25 (32 MiB)
        +-- CHR A25 (32 MiB)
      ||+-- CHR A25 (32 MiB)
      |+--- PRG A26 (64 MiB)
      +---- CHR A26 (64 MiB)
 
==Outer Bank Register 2 ($412E)==
7654 3210
---------
.... ...B
        +- PRG/CHR A27 (128 MiB)


=Two-channel PCM expansion sound=
=Two-channel PCM expansion sound=

Latest revision as of 14:37, 12 September 2022

NES 2.0 Mapper is used for the FC Pocket RS-20 and dreamGEAR My Arcade Gamer V handheld consoles. They use VT3x hardware, which is mostly compatible hardware to the earlier VT0x and VT1x consoles, but add an outer bank register and extended support for legacy mappers. While the original OneBus hardware only has MMC3-compatible registers, this type can directly emulate CNROM, UNROM and MMC1 behavior as well.

Banking registers

Mapper Configuration Register ($411D, write)

7654 3210
---------
.... .CMM
      |++- Select legacy mapper to emulate in the $8000-$FFFF range
      |     0: MMC3
      |     1: MMC1
      |     2: UNROM
      |     3: CNROM
      +--- Select CHR memory type
            0: CHR-ROM (banked)
            1: CHR-RAM (unbanked)

Encryption Control ($411E, write)

7654 3210
---------
cc.. .C.C
||    +-+- 00: Disable CPU opcode encryption after the next JMP instruction
||         11: Enable CPU opcode encryption after the next JMP instruction
++-------- 00: Disable CHR data encryption
           11: Enable CHR data encryption
  • When CPU encryption is active, CPU opcode bytes only are XORed with $A1.
  • When CHR data encryption is active, CHR data bytes' bits 0 and 4, 1 and 2, 3 and 7, and 5 and 6 are swapped.

Outer Bank Register ($412C)

7654 3210
---------
.... cpCP
     |||+- PRG A25 (32 MiB)
     ||+-- CHR A25 (32 MiB)
     |+--- PRG A26 (64 MiB)
     +---- CHR A26 (64 MiB)

Outer Bank Register 2 ($412E)

7654 3210
---------
.... ...B
        +- PRG/CHR A27 (128 MiB)

Two-channel PCM expansion sound

Expansion sound involves two simultaneous linear 8 bit unsigned PCM channels which just keep playing from their current address until byte $FF is encountered. Note that the address (excluding bits 0-5) is programmed directly and not relative to other bankswitching registers except the 32 MiB outer bank. The playback rate is set using the normal $4010 register bits 0-3.

Select channel 0 and set volume ($4031, write), Select channel 1 and set volume ($4032, write)

Selects the channel to which the next writes to $4012, $4035 and $4036 will apply, and sets its linear volume (0-255).

Expansion sound and channel enable ($4033, write)

7654 3210
---------
E..0 1...
|  | +---- 1=Enable channel 1
|  +------ 1=Enable channel 0
+--------- 1=Enable expansion sound

Note that the order of the channel bits is reversed from $4014 (see below).

Select playback address bits 6-13 ($4012), bits 14-20 ($4035), bits 21-28 ($4036)

These registers can only be accessed if expansion sound is enabled (via $4033 bit 7, otherwise it $4012 will go to the regular DPCM channel register), and if the selected channel has been disabled via the respective bit in $4033, otherwise the write will be ignored.

Channel status ($4014, read)

7654 3210
---------
.... ..10
       |+- 1=Channel 0 still playing
       +-- 1=Channel 1 still playing

These bits can be used to detect when a sample has finished playing (having encountered byte $FF) in order to restart it. Once a sample has finished playing, these bits return zero, and the channels are no longer enabled. Note that the FC Pocket RS-20 menu apparently confuses the two channel bits and continuously writes to restart the background music, which however does not actually occur because the hardware blocks accesss to the playback address registers while the sample is still playing.

Palette

While the original VT03+ Enhanced Palette uses four bits each for hue, saturation and luminance, the VT3x 12-bit palette simply directly encodes 4-bit RGB values:

BA98 7654 3210
--------------
BBBB GGGG RRRR
|||| |||| ++++- Red level (0-15)
|||| ++++------ Green level (0-15)
++++----------- Blue level (0-15)

The dreamGEAR My Arcade Gamer V multicart contains a few games that were previously published on VT03 multicarts. When converting these games to VT3x, the developers apparently forgot to change a few colors to the new format, resulting in some elements using strange color combinations even on real hardware (e.g. the waterfall in Curly Monkey).