NES 2.0 Mapper 304: Difference between revisions
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* ''Super Mario Bros. 2 (J)'' (Whirlwind Manu LE10, [https://archive.org/details/youtube-M2-ovBQW978 hangs after completing level 4-4 on real hardware]) | * ''Super Mario Bros. 2 (J)'' (Whirlwind Manu LE10, [https://archive.org/details/youtube-M2-ovBQW978 hangs after completing level 4-4 on real hardware]) | ||
* ''Volleyball (J)'' ( | * ''Volleyball (J)'' (Whirlwind Manu LE08) | ||
* ''Zanac (J)'' (Whirlwind Manu LF11) | * ''Zanac (J)'' (Whirlwind Manu LF11) | ||
FCEUX' source code says that the PCB for both the CHR-ROM and CHR-RAM variants is named ''09-034A''. | |||
=Banks= | =Banks= | ||
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=Registers= | =Registers= | ||
==PRG Bank Select ($4027)== | ==Unknown Registers ($4042-$4055, read)== | ||
Reading from these addresses must return $FF rather than open bus, otherwise SMB2J will freeze. | |||
==PRG Bank Select ($4027, write)== | |||
Mask: Unknown | Mask: Unknown | ||
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On games with only 32 KiB ROM, $6000-$7FFF will (as usual) wrap to banks #0 and #1. | On games with only 32 KiB ROM, $6000-$7FFF will (as usual) wrap to banks #0 and #1. | ||
==IRQ Control ($4068)== | ==IRQ Control ($4068, write)== | ||
Mask: Unknown | Mask: Unknown | ||
Latest revision as of 09:56, 1 May 2018
NES 2.0 Mapper 304 is used for several ROM cartridge conversions of Famicom Disk Systems for which, along with the entirely-different INES Mapper 043 and NES 2.0 Mapper 311, UNIF MAPR UNL-SMB2J is used.
- Super Mario Bros. 2 (J) (Whirlwind Manu LE10, hangs after completing level 4-4 on real hardware)
- Volleyball (J) (Whirlwind Manu LE08)
- Zanac (J) (Whirlwind Manu LF11)
FCEUX' source code says that the PCB for both the CHR-ROM and CHR-RAM variants is named 09-034A.
Banks
- CPU $6000-$7FFF: Switchable 8 KiB PRG-ROM bank (#4-#5)
- CPU $8000-$FFFF: Fixed 32 KiB PRG-ROM bank #0
- PPU $0000-$1FFF: Unbanked 8 KiB CHR-ROM or CHR-RAM.
Registers
Unknown Registers ($4042-$4055, read)
Reading from these addresses must return $FF rather than open bus, otherwise SMB2J will freeze.
PRG Bank Select ($4027, write)
Mask: Unknown
Bit 7654 3210
---------
.... ...B
+- 0: CPU $6000-$7FFF to 8 KiB bank #4
1: CPU $6000-$7FFF to 8 KiB bank #5
On games with only 32 KiB ROM, $6000-$7FFF will (as usual) wrap to banks #0 and #1.
IRQ Control ($4068, write)
Mask: Unknown
Bit 7654 3210
---------
.... ...I
+- 0: Disable and Acknowledge IRQ, and reset counter
1: Enable IRQ
According to FCEUX, when enabled, IRQ counter increases on every M2 cycle until it reaches 5750, upon which an IRQ is fired. While this does work nicely with the ROM image of LE10, the hardware video recording seems to indicate that the actual hardware does not have a functioning IRQ counter.
