NES 2.0 Mapper 520: Difference between revisions
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+---- Select outer 256 KiB PRG-ROM bank when PPU $0000-$03FF is accessed | +---- Select outer 256 KiB PRG-ROM bank when PPU $0000-$03FF is accessed | ||
* The high CHR Select register ($ | * The high CHR Select register ($B004) is ignored. | ||
* The other seven low CHR bank select registers continue the pattern for the other seven 1 KiB PPU banks. | * The other seven low CHR bank select registers continue the pattern for the other seven 1 KiB PPU banks. | ||
== Notes == | == Notes == | ||
* The ROM image in GoodNES 3.23b is set to Mapper 23, even as the outer bank register is not part of that mapper's specification. | * The ROM image in GoodNES 3.23b is set to Mapper 23, even as the outer bank register is not part of that mapper's specification. | ||
* As with [[MMC1#SOROM.2C_SUROM_and_SXROM|SOROM, SUROM and SXROM]], if the several CHR bank registers do not specify the same outer PRG ROM bank, then PRG ROM presumably would be bankswitched as the PPU renders. | * As with [[MMC1#SOROM.2C_SUROM_and_SXROM|SOROM, SUROM and SXROM]], if the several CHR bank registers do not specify the same outer PRG ROM bank, then PRG ROM presumably would be bankswitched as the PPU renders. | ||
Revision as of 10:13, 14 March 2018
NES 2.0 Mapper 520 is used for 2-in-1 Datach Dragon Ball Z/Datach Yu Yu Hakusho multicart. It uses a VRC4 clone (in the VRC4e configuration, i.e. address 0x004s to A0 and address 0x008s to A1) using 8 KiB of banked CHR-RAM rather than CHR-ROM:
CHR Select 0 low ($B000)
7 bit 0
---------
.... OLLL
|+++- Select 1 KiB CHR-RAM bank at PPU $0000-$03FF
+---- Select outer 256 KiB PRG-ROM bank when PPU $0000-$03FF is accessed
- The high CHR Select register ($B004) is ignored.
- The other seven low CHR bank select registers continue the pattern for the other seven 1 KiB PPU banks.
Notes
- The ROM image in GoodNES 3.23b is set to Mapper 23, even as the outer bank register is not part of that mapper's specification.
- As with SOROM, SUROM and SXROM, if the several CHR bank registers do not specify the same outer PRG ROM bank, then PRG ROM presumably would be bankswitched as the PPU renders.
