Namcot 108 family pinout

Namcot 108, 109, 118, 119: 28-pin shrink PDIP, also Tengen 337001 or MIMIC-1: 28-pin 0.6" PDIP (Canonically mapper 206).

               .--\/--.
(f) CPU A14 -> |01  28| -> PRG A15 (r)
(fr) CPU A0 -> |02  27| -> PRG A14 (r)
(fr) CPU D5 -> |03  26| <- M2 (f)      
(fr) CPU D0 -> |04  25| -> PRG A13 (r)
(fr) CPU D4 -> |05  24| <- CPU A13 (f)
(fr) CPU D1 -> |06  23| -> PRG A16 (r)
        Gnd -- |07  22| -> PRG /CE (r)
(fr) CPU D3 -> |08  21| -- +5V
(fr) CPU D2 -> |09  20| -> CHR A13 (r)
(f) /ROMSEL*-> |10  19| -> CHR A11 (r)
    (f) R/W -> |11  18| -> CHR A10 (r)
(r) CHR A15 <- |12  17| <- PPU A10 (f)
(r) CHR A14 <- |13  16| <- PPU A11 (f)
(r) CHR A12 <- |14  15| <- PPU A12 (f)
               `------'

10: on the Vs. System daughterboards, this is instead CPU /A15

No behavioral differences are known between the five different part numbers; several games were released on the same board with identical code and different mapper ICs.

Many boards (and thus iNES mappers) redefined parts of the pinout for various extensions, mostly to increase the amount of addressable CHR ROM.

Mapper 76:

(fr) CPU D2 -> |09  20| -> CHR A14 (r)
(f) /ROMSEL -> |10  19| -> CHR A12 (r)
    (f) R/W -> |11  18| -> CHR A11 (r)
(r) CHR A16 <- |12  17| <- PPU A11 (f)
(r) CHR A15 <- |13  16| <- PPU A12 (f)
(r) CHR A13 <- |14  15| <- +5V
               `------'

      (f) PPU A10 -> CHR A10 (r)

Mappers 88 and 154 connect (f) PPU A12 -> CHR A16 (r), skipping the mapper IC altogether.

Mapper 95:

(f) CIRAM A10 <- |12  17| <- PPU A10 (f)
  (r) CHR A14 <- |13  16| <- PPU A11 (f)
  (r) CHR A12 <- |14  15| <- PPU A12 (f)
                 `------'

---

Pirate clones of the Namco 108: AX-24G or NTDEC8701: 28-pin 0.6" PDIP

               .--\/--.
(r) PRG A13 <- |01  28| <- CPU A14 (f)
(r) PRG A14 <- |02  27| <- CPU A13 (f)
(r) PRG A16 <- |03  26| <- CPU A0 (fr)
(r) PRG A15 <- |04  25| -- VCC		 
(r) CHR A14 <- |05  24| <- /ROMSEL (f)
(r) CHR A11 <- |06  23| -> PRG /OE (r)
(r) CHR A13 <- |07  22| <- M2 (f)
(r) CHR A12 <- |08  21| <- R/W (f)
(fr) CPU D2 -> |09  20| <- CPU-D0 (fr)
(fr) CPU D3 -> |10  19| <- CPU-D5 (fr)
(fr) CPU D1 -> |11  18| <- CPU-D4 (fr)
        Gnd -- |12  17| <- PPU-A12 (f)
(r) CHR A15 <- |13  16| <- PPU-A11 (f)
(r) CHR A10 <- |14  15| <- PPU-A10 (f)
               `------'

source: https://forums.nesdev.org/viewtopic.php?p=210278#p210278