RP2C33 pinout: Difference between revisions

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m (pins 24, 53, 61, 62, 63 directions known from die photo ... not completely certain I've got the xtal driver correct)
(switch to webarchive for electronics junker's schematic)
 
(5 intermediate revisions by 3 users not shown)
Line 12: Line 12:
     (f) CPU A8 -> | 08  57 | <- R/W (rf)
     (f) CPU A8 -> | 08  57 | <- R/W (rf)
  (r) PRG A6/13 <- | 09  56 | <- M2 (Rf)
  (r) PRG A6/13 <- | 09  56 | <- M2 (Rf)
  (r) PRG A5/12 <- | 10  55 | -> /IRQ (f)
  (r) PRG A5/12 <- | 10  55 | +> /IRQ (f)
  (r) PRG A4/11 <- | 11  54 | -> Audio (f)
  (r) PRG A4/11 <- | 11  54 | -> Audio (f)
  (r) PRG A3/10 <- | 12  53 | <- ? (gnd)
  (r) PRG A3/10 <- | 12  53 | <- ? (gnd)
   (r) PRG A2/9 <- | 13  52 | -> SER OUT
   (r) PRG A2/9 <- | 13  52 | +> SER OUT
   (r) PRG A1/8 <- | 14  51 | <- SER IN
   (r) PRG A1/8 <- | 14  51 | <- SER IN
     (r) PRG A0 <- | 15  50 | -> $4025W.2 (Disk 1=Read, 0=Write)
     (r) PRG A0 <- | 15  50 | +> $4025W.2 (Disk 1=Read, 0=Write)
   (rf) CPU A7 -> | 16  49 | -> $4025W.1 (1=Reset transfer timing)
   (rf) CPU A7 -> | 16  49 | +> $4025W.1 (1=Reset transfer timing)
     (f) CPU A6 -> | 17  48 | -> $4025W.0 (1=Turn on motor)
     (f) CPU A6 -> | 17  48 | +> $4025W.0 (1=Turn on motor)
     (f) CPU A5 -> | 18  47 | <- $4032R.2 (1=Write protected)
     (f) CPU A5 -> | 18  47 | <- $4032R.2 (1=Write protected)
     (f) CPU A4 -> | 19  46 | <- $4032R.1 (1=Disk not ready)
     (f) CPU A4 -> | 19  46 | <- $4032R.1 (1=Disk not ready)
     (f) CPU A3 -> | 20  45 | <- $4032R.0 (1=Disk missing)
     (f) CPU A3 -> | 20  45 | <- $4032R.0 (1=Disk missing)
     (f) CPU A2 -> | 21  44 | <> EXT0
     (f) CPU A2 -> | 21  44 | <+> EXT0
     (f) CPU A1 -> | 22  43 | <> EXT1
     (f) CPU A1 -> | 22  43 | <+> EXT1
     (f) CPU A0 -> | 23  42 | <> EXT2
     (f) CPU A0 -> | 23  42 | <+> EXT2
             ? <- | 24  41 | <> EXT3
             ? <- | 24  41 | <+> EXT3
   (rf) CPU D0 <> | 25  40 | <> EXT4
   (rf) CPU D0 <> | 25  40 | <+> EXT4
   (rf) CPU D1 <> | 26  39 | <> EXT5
   (rf) CPU D1 <> | 26  39 | <+> EXT5
   (rf) CPU D2 <> | 27  38 | <> EXT6
   (rf) CPU D2 <> | 27  38 | <+> EXT6
   (rf) CPU D3 <> | 28  37 | <> EXT7/BATT
   (rf) CPU D3 <> | 28  37 | <+> EXT7/BATT
   (rf) CPU D4 <> | 29  36 | <- PPU A10 (f)
   (rf) CPU D4 <> | 29  36 | <- PPU A10 (f)
   (rf) CPU D5 <> | 30  35 | <- PPU A11 (f)
   (rf) CPU D5 <> | 30  35 | <- PPU A11 (f)
Line 39: Line 39:
  r - connects to DRAM (all revisions)
  r - connects to DRAM (all revisions)
  f - connects to Famicom
  f - connects to Famicom
+ - output is open-drain, requires an external pull-up resistor
Expansion audio mixing circuit schematic:
                              1.2M
                          +---/\/---+
                +        |        |      56K
From RP2C33---||---/\/---+---|>o---+---+---/\/---+
(RP2C33.54)  1u    2M                |        |
                                  0.1u ---        |
                                      ---        |
                                        |        |            100K
                                      GND        |        +---/\/---+
                                                  |    +  |        |
From 2A03----------------------------------/\/---+---||---+---|>o---+---To RF
(Cart.45)                                  56K      1u              (Cart.46)


Notes:
Notes:
Line 44: Line 59:
* EXT port can be written via $4026 and read via $4033
* EXT port can be written via $4026 and read via $4033


Transcribed from http://green.ap.teacup.com/junker/119.html
Transcribed from https://web.archive.org/web/20140920224500/green.ap.teacup.com/junker/119.html

Latest revision as of 12:39, 25 March 2024

Family Computer Disk System ASIC RP2C33 or RP2C33A: 64-pin shrink DIP (FDS files)

                 .---\/---.
 (Rf) /ROMSEL -> | 01  64 | -- +5V
 (Rf) CPU A14 -> | 02  63 | <- XTAL2
 (Rf) CPU A13 -> | 03  62 | -> XTAL1
  (f) CPU A12 -> | 04  61 | <- ? (gnd)
  (f) CPU A11 -> | 05  60 | -> /RAS (r)
  (f) CPU A10 -> | 06  59 | -> /CAS1 (r)
   (f) CPU A9 -> | 07  58 | -> /CAS0 (r)
   (f) CPU A8 -> | 08  57 | <- R/W (rf)
(r) PRG A6/13 <- | 09  56 | <- M2 (Rf)
(r) PRG A5/12 <- | 10  55 | +> /IRQ (f)
(r) PRG A4/11 <- | 11  54 | -> Audio (f)
(r) PRG A3/10 <- | 12  53 | <- ? (gnd)
 (r) PRG A2/9 <- | 13  52 | +> SER OUT
 (r) PRG A1/8 <- | 14  51 | <- SER IN
   (r) PRG A0 <- | 15  50 | +> $4025W.2 (Disk 1=Read, 0=Write)
  (rf) CPU A7 -> | 16  49 | +> $4025W.1 (1=Reset transfer timing)
   (f) CPU A6 -> | 17  48 | +> $4025W.0 (1=Turn on motor)
   (f) CPU A5 -> | 18  47 | <- $4032R.2 (1=Write protected)
   (f) CPU A4 -> | 19  46 | <- $4032R.1 (1=Disk not ready)
   (f) CPU A3 -> | 20  45 | <- $4032R.0 (1=Disk missing)
   (f) CPU A2 -> | 21  44 | <+> EXT0
   (f) CPU A1 -> | 22  43 | <+> EXT1
   (f) CPU A0 -> | 23  42 | <+> EXT2
            ? <- | 24  41 | <+> EXT3
  (rf) CPU D0 <> | 25  40 | <+> EXT4
  (rf) CPU D1 <> | 26  39 | <+> EXT5
  (rf) CPU D2 <> | 27  38 | <+> EXT6
  (rf) CPU D3 <> | 28  37 | <+> EXT7/BATT
  (rf) CPU D4 <> | 29  36 | <- PPU A10 (f)
  (rf) CPU D5 <> | 30  35 | <- PPU A11 (f)
  (rf) CPU D6 <> | 31  34 | -> CIRAM A10 (f)
          GND -- | 32  33 | <> CPU D7 (rf)
                 '--------'
R - connects to LH2833 DRAM in later PCB revisions
r - connects to DRAM (all revisions)
f - connects to Famicom
+ - output is open-drain, requires an external pull-up resistor

Expansion audio mixing circuit schematic:
                             1.2M
                         +---/\/---+
                +        |         |       56K
From RP2C33---||---/\/---+---|>o---+---+---/\/---+
(RP2C33.54)   1u    2M                 |         |
                                 0.1u ---        |
                                      ---        |
                                       |         |            100K
                                      GND        |        +---/\/---+
                                                 |     +  |         |
From 2A03----------------------------------/\/---+---||---+---|>o---+---To RF
(Cart.45)                                  56K      1u              (Cart.46)

Notes:

  • PRG address bus is multiplexed, as is typical for DRAMs.
  • EXT port can be written via $4026 and read via $4033

Transcribed from https://web.archive.org/web/20140920224500/green.ap.teacup.com/junker/119.html