RP2C33 pinout

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Revision as of 22:38, 5 October 2016 by Lidnariq (talk | contribs) (transcribe from electronics junker's schematic)
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RP2C33 and RP2C33A: 64-pin shrink DIP (FDS files)

              .---\/---.
   /ROMSEL -> | 01  64 | -- +5V
   CPU A14 -> | 02  63 | ?? XTAL2
   CPU A13 -> | 03  62 | ?? XTAL1
   CPU A12 -> | 04  61 | -- Gnd
   CPU A11 -> | 05  60 | -> /RAS
   CPU A10 -> | 06  59 | -> /CAS1
    CPU A9 -> | 07  58 | -> /CAS0
    CPU A8 -> | 08  57 | <- R/W
 PRG A6/14 <- | 09  56 | <- M2
 PRG A5/13 <- | 10  55 | -> /IRQ
 PRG A4/12 <- | 11  54 | -> Audio		 
 PRG A3/11 <- | 12  53 | -- Gnd			
 PRG A2/10 <- | 13  52 | -> SER OUT	
  PRG A1/9 <- | 14  51 | <- SER IN		
  PRG A0/8 <- | 15  50 | -> $4025W.2 (Disk 1=Read, 0=Write)
    CPU A7 -> | 16  49 | -> $4025W.1 (1=Reset transfer timing)
    CPU A6 -> | 17  48 | -> $4025W.0 (1=Turn on motor)
    CPU A5 -> | 18  47 | <- $4032R.2 (1=Write protected)
    CPU A4 -> | 19  46 | <- $4032R.1 (1=Disk not ready)
    CPU A3 -> | 20  45 | <- $4032R.0 (1=Disk missing)
    CPU A2 -> | 21  44 | <> EXT0			
    CPU A1 -> | 22  43 | <> EXT1			
    CPU A0 -> | 23  42 | <> EXT2			
         ? ?? | 24  41 | <> EXT3			
    CPU D0 <> | 25  40 | <> EXT4			
    CPU D1 <> | 26  39 | <> EXT5			
    CPU D2 <> | 27  38 | <> EXT6			
    CPU D3 <> | 28  37 | <> EXT7/BATT
    CPU D4 <> | 29  36 | <- PPU A10	
    CPU D5 <> | 30  35 | <- PPU A11	
    CPU D6 <> | 31  34 | -> CIRAM A10
       GND -- | 32  33 | <> CPU D7
              '--------'

Notes:
 PRG address bus is multiplexed, as is typical for DRAMs.
 EXT port can be written via $4026 and read via $4033


Transcribed from http://green.ap.teacup.com/junker/119.html