User contributions for Ndwiki
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11 June 2009
- 14:0514:05, 11 June 2009 diff hist +2,845 Nm PPU sprite evaluation Created page with 'During all visible scanlines, the PPU scans through OAM to determine which sprites to render on the next scanline. During each pixel clock (341 total per scanline), the PPU acces...'
- 14:0514:05, 11 June 2009 diff hist +46 m PPU No edit summary
- 14:0414:04, 11 June 2009 diff hist +1,892 Nm PPU sprite priority Created page with 'In the NES PPU, each sprite has two values that affect '''priority''', or what appears behind what: the index of the sprite within OAM (0 to 63), and the prio...'
- 14:0314:03, 11 June 2009 diff hist +42 m PPU No edit summary
- 14:0014:00, 11 June 2009 diff hist −53 m NMI No edit summary
- 13:5913:59, 11 June 2009 diff hist −3 m NMI No edit summary
- 13:5813:58, 11 June 2009 diff hist +36 m PPU No edit summary
- 13:5713:57, 11 June 2009 diff hist +2,591 Nm PPU frame timing Created page with 'The following behavior is tested by the ppu_vbl_nmi_timing test ROMs. Only the NTSC PPU is covered, though most probably applies to the PAL PPU. == Even/Odd F...'
- 13:5613:56, 11 June 2009 diff hist 0 m NMI No edit summary
- 13:5513:55, 11 June 2009 diff hist −6 m 2A03 Created page with 'The '''2A03''', short for RP2A03[G], is the common name of the NTSC NES CPU chip. It consists of a MOS Technology 6502 processor (lacking decimal mode) and audio generati...'
- 13:5313:53, 11 June 2009 diff hist +1 m PPU No edit summary
- 13:5313:53, 11 June 2009 diff hist +3,103 Nm NMI Created page with 'The 2A03 and most other 6502 family CPUs are capable of processing a '''non-maskable interrupt''' ('''NMI'''). This input is edge-sensitive, meaning that if other circuitry o...'
- 13:4913:49, 11 June 2009 diff hist +13 m PPU →Hardware behaviors
- 13:4713:47, 11 June 2009 diff hist −7 m PPU registers No edit summary
- 13:4013:40, 11 June 2009 diff hist −47 m PPU registers No edit summary
- 13:2713:27, 11 June 2009 diff hist +71 m PPU registers No edit summary
- 13:1913:19, 11 June 2009 diff hist −11 m PPU registers →Controller ($2000) [write]
- 13:1913:19, 11 June 2009 diff hist +16 m PPU registers →Controller ($2000) [write]
- 13:1813:18, 11 June 2009 diff hist +4 m PPU registers →Controller ($2000) [write]
- 13:1113:11, 11 June 2009 diff hist +9 m PPU registers No edit summary