User contributions for Quietust
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7 April 2021
- 02:4602:46, 7 April 2021 diff hist +1 m PPU scrolling →Tile and attribute fetching
- 02:3802:38, 7 April 2021 diff hist +2 m PPU scrolling →Register controls: Also change "=" to "<-" to more clearly express that the values are being transferred (already updated the others above but missed these two)
- 02:3502:35, 7 April 2021 diff hist +128 PPU scrolling →Register controls: Adjust the diagrams for the various writes - order them ABCDEFGH (instead of HGFEDCBA) and mark unused bits. For the H/V updates, label the various bits according to their logical positions rather than their literal locations
26 March 2021
- 18:1318:13, 26 March 2021 diff hist +50 m Colour emphasis explain why they become unplayable current
24 March 2021
- 20:1920:19, 24 March 2021 diff hist +86 m Mapper →Common capabilities: mention Konami's ASIC mappers too
23 March 2021
- 20:5920:59, 23 March 2021 diff hist +27 m PPU pinout No edit summary
- 20:5720:57, 23 March 2021 diff hist +100 m PPU pinout Then again, I suppose it could go either way...
- 20:5620:56, 23 March 2021 diff hist +82 PPU pinout →Signal description: A dual-PPU system would have no use for genlock, but if you're using $2000.6 and the EXT pins then you'd absolutely want to keep them perfectly synchronized with each other
- 20:3220:32, 23 March 2021 diff hist −19 m PPU pinout →Signal description: siliconpr0n has a top-layer image of an RP2C04-0003, and EXT3 is connected directly to GND inside the chip.
19 February 2021
- 02:0402:04, 19 February 2021 diff hist +60 VRC7 pinout Visual analysis confirms that pin 48 *is* derived solely from pins 1 and 2, but it's hard to tell exactly what's going on.
17 February 2021
- 17:5517:55, 17 February 2021 diff hist +6 J.Y. Company ASIC Yes, the title screen actually says "PEPOLE
21 January 2021
- 16:2116:21, 21 January 2021 diff hist +5 m CPU Test Mode No edit summary
- 16:2016:20, 21 January 2021 diff hist +4 m CPU Test Mode The bottom 5 bits of W$401A don't set the "instant phase" - they set the state of the triangle's Sequencer (i.e. $07 and $18 will result in the same effective output)
- 15:5815:58, 21 January 2021 diff hist +35 CPU Test Mode Setting $401A.7 makes the pulse and noise channels output their current volume (even if disabled via length counter), pauses the triangle channel's counter, and stops DPCM from counting up or down
3 December 2020
- 15:0115:01, 3 December 2020 diff hist +101 Family Computer Disk System →Hardware: Clean this up a bit
27 November 2020
- 02:5402:54, 27 November 2020 diff hist 0 m PPU palettes →2C04: 2C04 is a PPU, not a CPU
9 November 2020
- 15:5815:58, 9 November 2020 diff hist −3 m NSF No edit summary
- 15:5115:51, 9 November 2020 diff hist −10 m Visual circuit tutorial No edit summary
- 15:4715:47, 9 November 2020 diff hist −19 m Errata No edit summary
- 15:4615:46, 9 November 2020 diff hist −26 m APU No edit summary
- 12:5912:59, 9 November 2020 diff hist −5 m MMC3 No edit summary
- 12:5412:54, 9 November 2020 diff hist −12 m PPU registers Bulleted lists shouldn't have blank lines between entries, otherwise each entry is rendered as its own distinct list
11 October 2020
- 20:2020:20, 11 October 2020 diff hist +313 m Cycle counting some extra details - explain RMW, and clarify that stack PUSH takes 1 extra cycle and stack POP takes two extra cycles
2 October 2020
- 13:3213:32, 2 October 2020 diff hist +6 m CPU pinout →Signal description: clarify that the actual duty cycle is 15/24, which happens to simplify to 5/8
25 September 2020
- 14:4214:42, 25 September 2020 diff hist +3 m PPU OAM →Dynamic RAM decay
6 September 2020
- 04:0504:05, 6 September 2020 diff hist 0 m VRC7 pinout the data pins are bidirectional, presumably only for debug mode
1 September 2020
- 13:1813:18, 1 September 2020 diff hist +89 PPU palettes →RC2C03B: clarify "color bits 0-1 are 01"
4 August 2020
- 20:5320:53, 4 August 2020 diff hist +174 Talk:Stack No edit summary current
- 20:5320:53, 4 August 2020 diff hist 0 Stack →Pulling values: fix comments to match code current
6 July 2020
- 03:1403:14, 6 July 2020 diff hist 0 m J.Y. Company ASIC →Example Games: typo
25 June 2020
- 17:1017:10, 25 June 2020 diff hist +2 m Emulator tests change links to HTTPS; I also just updated the formatting of the "PPU" column
20 May 2020
- 21:4721:47, 20 May 2020 diff hist +364 Talk:Bandai FCG board No edit summary current
- 21:3521:35, 20 May 2020 diff hist +431 Talk:Bandai FCG board No edit summary
- 15:4215:42, 20 May 2020 diff hist +60 m Talk:Bandai FCG board No edit summary
- 15:4115:41, 20 May 2020 diff hist +701 Talk:Bandai FCG board No edit summary
13 May 2020
- 13:1913:19, 13 May 2020 diff hist +45 m Visual 2C02 →Navigation (section 6)
- 13:1813:18, 13 May 2020 diff hist +106 Visual 2C02 →Navigation (section 6)
7 May 2020
- 21:2121:21, 7 May 2020 diff hist +6 m Visual 2C02 →Navigation (section 6)
- 21:1321:13, 7 May 2020 diff hist +523 Visual 2C02 →Section overview: update documentation
- 20:5520:55, 7 May 2020 diff hist 0 File:Visual 2C02 sections.jpeg Quietust uploaded a new version of File:Visual 2C02 sections.jpeg current
- 13:3713:37, 7 May 2020 diff hist +2 m Visual 2C02 https
- 13:3613:36, 7 May 2020 diff hist +418 Visual 2C02 the "unused box" is actually used now - it shows the pixels being rendered, using an RGB palette (though it doesn't emulate Emphasis yet)
25 April 2020
- 02:3102:31, 25 April 2020 diff hist 0 m PPU variants No edit summary
18 April 2020
- 03:1403:14, 18 April 2020 diff hist +1 m APU DMC form -> forum
10 April 2020
- 02:1602:16, 10 April 2020 diff hist +51 m APU Noise clarify: in early chips, the Mode flag didn't even '''exist''', so there was nothing to "ignore"
9 April 2020
- 16:3116:31, 9 April 2020 diff hist +118 NTSC video →Scanline Timing: add an image to better visualize the scanline timing tables
- 16:2916:29, 9 April 2020 diff hist +27 File:Ntsc video timing.png No edit summary
- 16:2916:29, 9 April 2020 diff hist 0 File:Ntsc video timing.png Quietust uploaded a new version of File:Ntsc video timing.png
- 16:2316:23, 9 April 2020 diff hist +570 N File:Ntsc video timing.png A visualization of the NTSC PPU's video output signal, using different colors to denote each part of the signal. * Cyan is the horizontal blanking pulse * Dark blue is the "front porch" ** Yellow is the colorburst signal * Red is the visible output re...
- 14:0014:00, 9 April 2020 diff hist +83 NTSC video merge and reword some awkwardly-short sentences
