User contributions for Quietust
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7 April 2021
- 02:4602:46, 7 April 2021 diff hist +1 m PPU scrolling →Tile and attribute fetching
- 02:3802:38, 7 April 2021 diff hist +2 m PPU scrolling →Register controls: Also change "=" to "<-" to more clearly express that the values are being transferred (already updated the others above but missed these two)
- 02:3502:35, 7 April 2021 diff hist +128 PPU scrolling →Register controls: Adjust the diagrams for the various writes - order them ABCDEFGH (instead of HGFEDCBA) and mark unused bits. For the H/V updates, label the various bits according to their logical positions rather than their literal locations
26 March 2021
- 18:1318:13, 26 March 2021 diff hist +50 m Colour emphasis explain why they become unplayable current
24 March 2021
- 20:1920:19, 24 March 2021 diff hist +86 m Mapper →Common capabilities: mention Konami's ASIC mappers too
23 March 2021
- 20:5920:59, 23 March 2021 diff hist +27 m PPU pinout No edit summary
- 20:5720:57, 23 March 2021 diff hist +100 m PPU pinout Then again, I suppose it could go either way...
- 20:5620:56, 23 March 2021 diff hist +82 PPU pinout →Signal description: A dual-PPU system would have no use for genlock, but if you're using $2000.6 and the EXT pins then you'd absolutely want to keep them perfectly synchronized with each other
- 20:3220:32, 23 March 2021 diff hist −19 m PPU pinout →Signal description: siliconpr0n has a top-layer image of an RP2C04-0003, and EXT3 is connected directly to GND inside the chip.
19 February 2021
- 02:0402:04, 19 February 2021 diff hist +60 VRC7 pinout Visual analysis confirms that pin 48 *is* derived solely from pins 1 and 2, but it's hard to tell exactly what's going on.
17 February 2021
- 17:5517:55, 17 February 2021 diff hist +6 J.Y. Company ASIC Yes, the title screen actually says "PEPOLE
21 January 2021
- 16:2116:21, 21 January 2021 diff hist +5 m CPU Test Mode No edit summary
- 16:2016:20, 21 January 2021 diff hist +4 m CPU Test Mode The bottom 5 bits of W$401A don't set the "instant phase" - they set the state of the triangle's Sequencer (i.e. $07 and $18 will result in the same effective output)
- 15:5815:58, 21 January 2021 diff hist +35 CPU Test Mode Setting $401A.7 makes the pulse and noise channels output their current volume (even if disabled via length counter), pauses the triangle channel's counter, and stops DPCM from counting up or down
3 December 2020
- 15:0115:01, 3 December 2020 diff hist +101 Family Computer Disk System →Hardware: Clean this up a bit
27 November 2020
- 02:5402:54, 27 November 2020 diff hist 0 m PPU palettes →2C04: 2C04 is a PPU, not a CPU
9 November 2020
- 15:5815:58, 9 November 2020 diff hist −3 m NSF No edit summary
- 15:5115:51, 9 November 2020 diff hist −10 m Visual circuit tutorial No edit summary
- 15:4715:47, 9 November 2020 diff hist −19 m Errata No edit summary
- 15:4615:46, 9 November 2020 diff hist −26 m APU No edit summary
