User contributions for Quietust
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3 June 2021
- 15:5615:56, 3 June 2021 diff hist −5 m Aladdin deck enhancer pinout "wire wire"
19 May 2021
- 14:2114:21, 19 May 2021 diff hist +1 m UNIF/UNL-DripGame No edit summary current
- 13:4713:47, 19 May 2021 diff hist −6 m UNIF/UNL-DripGame No edit summary
17 May 2021
- 13:3713:37, 17 May 2021 diff hist +1 m File:2a03 map.jpg update URL to https current
6 May 2021
- 15:2915:29, 6 May 2021 diff hist +8 m MMC1 →CHR bank 0 (internal, $A000-$BFFF): fix copy/paste error - only the lowest bit is ignored in 8KB mode
23 April 2021
- 12:5812:58, 23 April 2021 diff hist +658 Talk:CPU addressing modes No edit summary current
14 April 2021
- 15:1315:13, 14 April 2021 diff hist +69 m Emulator tests Clarify why my emulator was used for the "known good" log - kevtris used it when he was writing the test, and its debug output is also reasonably detailed
7 April 2021
- 02:5402:54, 7 April 2021 diff hist +8 m Famicom Network System for completeness, repeat the "$0027 = ~33ms" here
- 02:4602:46, 7 April 2021 diff hist +1 m PPU scrolling →Tile and attribute fetching
- 02:3802:38, 7 April 2021 diff hist +2 m PPU scrolling →Register controls: Also change "=" to "<-" to more clearly express that the values are being transferred (already updated the others above but missed these two)
- 02:3502:35, 7 April 2021 diff hist +128 PPU scrolling →Register controls: Adjust the diagrams for the various writes - order them ABCDEFGH (instead of HGFEDCBA) and mark unused bits. For the H/V updates, label the various bits according to their logical positions rather than their literal locations
26 March 2021
- 18:1318:13, 26 March 2021 diff hist +50 m Colour emphasis explain why they become unplayable current
24 March 2021
- 20:1920:19, 24 March 2021 diff hist +86 m Mapper →Common capabilities: mention Konami's ASIC mappers too
23 March 2021
- 20:5920:59, 23 March 2021 diff hist +27 m PPU pinout No edit summary
- 20:5720:57, 23 March 2021 diff hist +100 m PPU pinout Then again, I suppose it could go either way...
- 20:5620:56, 23 March 2021 diff hist +82 PPU pinout →Signal description: A dual-PPU system would have no use for genlock, but if you're using $2000.6 and the EXT pins then you'd absolutely want to keep them perfectly synchronized with each other
- 20:3220:32, 23 March 2021 diff hist −19 m PPU pinout →Signal description: siliconpr0n has a top-layer image of an RP2C04-0003, and EXT3 is connected directly to GND inside the chip.
19 February 2021
- 02:0402:04, 19 February 2021 diff hist +60 VRC7 pinout Visual analysis confirms that pin 48 *is* derived solely from pins 1 and 2, but it's hard to tell exactly what's going on.
17 February 2021
- 17:5517:55, 17 February 2021 diff hist +6 J.Y. Company ASIC Yes, the title screen actually says "PEPOLE
21 January 2021
- 16:2116:21, 21 January 2021 diff hist +5 m CPU Test Mode No edit summary